Loading drivers/thunderbolt/dma_test.c +4 −4 Original line number Diff line number Diff line Loading @@ -192,9 +192,9 @@ static int dma_test_start_rings(struct dma_test *dt) } ret = tb_xdomain_enable_paths(dt->xd, dt->tx_hopid, dt->tx_ring ? dt->tx_ring->hop : 0, dt->tx_ring ? dt->tx_ring->hop : -1, dt->rx_hopid, dt->rx_ring ? dt->rx_ring->hop : 0); dt->rx_ring ? dt->rx_ring->hop : -1); if (ret) { dma_test_free_rings(dt); return ret; Loading @@ -218,9 +218,9 @@ static void dma_test_stop_rings(struct dma_test *dt) tb_ring_stop(dt->tx_ring); ret = tb_xdomain_disable_paths(dt->xd, dt->tx_hopid, dt->tx_ring ? dt->tx_ring->hop : 0, dt->tx_ring ? dt->tx_ring->hop : -1, dt->rx_hopid, dt->rx_ring ? dt->rx_ring->hop : 0); dt->rx_ring ? dt->rx_ring->hop : -1); if (ret) dev_warn(&dt->svc->dev, "failed to disable DMA paths\n"); Loading drivers/thunderbolt/nhi.c +8 −3 Original line number Diff line number Diff line Loading @@ -56,10 +56,15 @@ static int ring_interrupt_index(const struct tb_ring *ring) static void nhi_mask_interrupt(struct tb_nhi *nhi, int mask, int ring) { if (nhi->quirks & QUIRK_AUTO_CLEAR_INT) return; if (nhi->quirks & QUIRK_AUTO_CLEAR_INT) { u32 val; val = ioread32(nhi->iobase + REG_RING_INTERRUPT_BASE + ring); iowrite32(val & ~mask, nhi->iobase + REG_RING_INTERRUPT_BASE + ring); } else { iowrite32(mask, nhi->iobase + REG_RING_INTERRUPT_MASK_CLEAR_BASE + ring); } } static void nhi_clear_interrupt(struct tb_nhi *nhi, int ring) { Loading drivers/thunderbolt/tb.c +12 −5 Original line number Diff line number Diff line Loading @@ -737,6 +737,7 @@ static void tb_scan_port(struct tb_port *port) { struct tb_cm *tcm = tb_priv(port->sw->tb); struct tb_port *upstream_port; bool discovery = false; struct tb_switch *sw; int ret; Loading Loading @@ -804,8 +805,10 @@ static void tb_scan_port(struct tb_port *port) * tunnels and know which switches were authorized already by * the boot firmware. */ if (!tcm->hotplug_active) if (!tcm->hotplug_active) { dev_set_uevent_suppress(&sw->dev, true); discovery = true; } /* * At the moment Thunderbolt 2 and beyond (devices with LC) we Loading Loading @@ -835,10 +838,14 @@ static void tb_scan_port(struct tb_port *port) * CL0s and CL1 are enabled and supported together. * Silently ignore CLx enabling in case CLx is not supported. */ if (discovery) { tb_sw_dbg(sw, "discovery, not touching CL states\n"); } else { ret = tb_switch_enable_clx(sw, TB_CL1); if (ret && ret != -EOPNOTSUPP) tb_sw_warn(sw, "failed to enable %s on upstream port\n", tb_switch_clx_name(TB_CL1)); } if (tb_switch_is_clx_enabled(sw, TB_CL1)) /* Loading drivers/thunderbolt/tunnel.c +1 −1 Original line number Diff line number Diff line Loading @@ -531,7 +531,7 @@ static int tb_dp_xchg_caps(struct tb_tunnel *tunnel) * Perform connection manager handshake between IN and OUT ports * before capabilities exchange can take place. */ ret = tb_dp_cm_handshake(in, out, 1500); ret = tb_dp_cm_handshake(in, out, 3000); if (ret) return ret; Loading Loading
drivers/thunderbolt/dma_test.c +4 −4 Original line number Diff line number Diff line Loading @@ -192,9 +192,9 @@ static int dma_test_start_rings(struct dma_test *dt) } ret = tb_xdomain_enable_paths(dt->xd, dt->tx_hopid, dt->tx_ring ? dt->tx_ring->hop : 0, dt->tx_ring ? dt->tx_ring->hop : -1, dt->rx_hopid, dt->rx_ring ? dt->rx_ring->hop : 0); dt->rx_ring ? dt->rx_ring->hop : -1); if (ret) { dma_test_free_rings(dt); return ret; Loading @@ -218,9 +218,9 @@ static void dma_test_stop_rings(struct dma_test *dt) tb_ring_stop(dt->tx_ring); ret = tb_xdomain_disable_paths(dt->xd, dt->tx_hopid, dt->tx_ring ? dt->tx_ring->hop : 0, dt->tx_ring ? dt->tx_ring->hop : -1, dt->rx_hopid, dt->rx_ring ? dt->rx_ring->hop : 0); dt->rx_ring ? dt->rx_ring->hop : -1); if (ret) dev_warn(&dt->svc->dev, "failed to disable DMA paths\n"); Loading
drivers/thunderbolt/nhi.c +8 −3 Original line number Diff line number Diff line Loading @@ -56,10 +56,15 @@ static int ring_interrupt_index(const struct tb_ring *ring) static void nhi_mask_interrupt(struct tb_nhi *nhi, int mask, int ring) { if (nhi->quirks & QUIRK_AUTO_CLEAR_INT) return; if (nhi->quirks & QUIRK_AUTO_CLEAR_INT) { u32 val; val = ioread32(nhi->iobase + REG_RING_INTERRUPT_BASE + ring); iowrite32(val & ~mask, nhi->iobase + REG_RING_INTERRUPT_BASE + ring); } else { iowrite32(mask, nhi->iobase + REG_RING_INTERRUPT_MASK_CLEAR_BASE + ring); } } static void nhi_clear_interrupt(struct tb_nhi *nhi, int ring) { Loading
drivers/thunderbolt/tb.c +12 −5 Original line number Diff line number Diff line Loading @@ -737,6 +737,7 @@ static void tb_scan_port(struct tb_port *port) { struct tb_cm *tcm = tb_priv(port->sw->tb); struct tb_port *upstream_port; bool discovery = false; struct tb_switch *sw; int ret; Loading Loading @@ -804,8 +805,10 @@ static void tb_scan_port(struct tb_port *port) * tunnels and know which switches were authorized already by * the boot firmware. */ if (!tcm->hotplug_active) if (!tcm->hotplug_active) { dev_set_uevent_suppress(&sw->dev, true); discovery = true; } /* * At the moment Thunderbolt 2 and beyond (devices with LC) we Loading Loading @@ -835,10 +838,14 @@ static void tb_scan_port(struct tb_port *port) * CL0s and CL1 are enabled and supported together. * Silently ignore CLx enabling in case CLx is not supported. */ if (discovery) { tb_sw_dbg(sw, "discovery, not touching CL states\n"); } else { ret = tb_switch_enable_clx(sw, TB_CL1); if (ret && ret != -EOPNOTSUPP) tb_sw_warn(sw, "failed to enable %s on upstream port\n", tb_switch_clx_name(TB_CL1)); } if (tb_switch_is_clx_enabled(sw, TB_CL1)) /* Loading
drivers/thunderbolt/tunnel.c +1 −1 Original line number Diff line number Diff line Loading @@ -531,7 +531,7 @@ static int tb_dp_xchg_caps(struct tb_tunnel *tunnel) * Perform connection manager handshake between IN and OUT ports * before capabilities exchange can take place. */ ret = tb_dp_cm_handshake(in, out, 1500); ret = tb_dp_cm_handshake(in, out, 3000); if (ret) return ret; Loading