Unverified Commit ee58c0a4 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'renesas-arm-dt-for-v5.17-tag1' of... 

Merge tag 'renesas-arm-dt-for-v5.17-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt

Renesas ARM DT updates for v5.17

  - Serial, SPI, timer, watchdog, operating points, and QSPI FLASH
    support for the RZ/G2L SoC and the RZ/G2L SMARC EVK development
    board,
  - SDHI SDnH clocks for the R-Car Gen3 and RZ/G2 SoCs,
  - Display Unit support for the R-Car V3U SoC,
  - Miscellaneous fixes and improvements.

* tag 'renesas-arm-dt-for-v5.17-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (21 commits)
  arm64: dts: renesas: r8a779a0: Add DU support
  arm64: dts: renesas: salvator-common: Merge hdmi0_con
  arm64: dts: renesas: ulcb: Merge hdmi0_con
  arm64: dts: renesas: r9a07g044: Add OPP table
  arm64: dts: renesas: Fix operating point table node names
  arm64: dts: renesas: rzg2l-smarc-som: Enable watchdog
  arm64: dts: renesas: r9a07g044: Add WDT nodes
  arm64: dts: renesas: r9a07g044: Rename SDHI clocks
  arm64: dts: renesas: rzg2l-smarc-som: Enable serial NOR flash
  arm64: dts: renesas: rzg2l-smarc-som: Enable OSTM
  arm64: dts: renesas: r9a07g044: Add OSTM nodes
  arm64: dts: renesas: r9a07g044: Sort psci node
  arm64: dts: renesas: rzg2l-smarc: Enable RSPI1 on carrier board
  arm64: dts: renesas: r9a07g044: Add RSPI{0,1,2} nodes
  arm64: dts: renesas: cat875: Add rx/tx delays
  arm64: dts: reneas: rcar-gen3: Add SDnH clocks
  arm64: dts: reneas: rzg2: Add SDnH clocks
  arm64: dts: renesas: r9a07g044: Add SCI[0-1] nodes
  arm64: dts: renesas: rzg2l-smarc: Enable SCIF2 on carrier board
  arm64: dts: renesas: r9a07g044: Add SCIF[1-4] nodes
  ...

Link: https://lore.kernel.org/r/cover.1638530606.git.geert+renesas@glider.be


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 7cf4cc3e cdda0194

arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts

+16 −0
Original line number Diff line number Diff line
@@ -44,6 +44,22 @@ mclk_cam4: mclk-cam4 { 
		#clock-cells = <0>;

		clock-frequency = <26000000>;

	};



	reg_1p8v: 1p8v {

		compatible = "regulator-fixed";

		regulator-name = "1P8V";

		regulator-min-microvolt = <1800000>;

		regulator-max-microvolt = <1800000>;

		regulator-always-on;

	};



	reg_2p8v: 2p8v {

		compatible = "regulator-fixed";

		regulator-name = "2P8V";

		regulator-min-microvolt = <2800000>;

		regulator-max-microvolt = <2800000>;

		regulator-always-on;

	};

};



&avb {

arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi

+3 −0
Original line number Diff line number Diff line
@@ -17,6 +17,9 @@ ov5640@3c { 
		reg = <0x3c>;

		clocks = <&MCLK_CAM>;

		clock-names = "xclk";

		AVDD-supply = <&reg_2p8v>;

		DOVDD-supply = <&reg_2p8v>;

		DVDD-supply = <&reg_1p8v>;

		status = "okay";



		port {

arch/arm64/boot/dts/renesas/cat875.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ &avb { 
	pinctrl-names = "default";

	renesas,no-ether-link;

	phy-handle = <&phy0>;

	phy-mode = "rgmii-id";

	status = "okay";



	phy0: ethernet-phy@0 {

arch/arm64/boot/dts/renesas/r8a774a1.dtsi

+10 −6
Original line number Diff line number Diff line
@@ -58,7 +58,7 @@ can_clk: can { 
		clock-frequency = <0>;

	};



	cluster0_opp: opp_table0 {

	cluster0_opp: opp-table-0 {

		compatible = "operating-points-v2";

		opp-shared;
@@ -80,7 +80,7 @@ opp-1500000000 { 
		};

	};



	cluster1_opp: opp_table1 {

	cluster1_opp: opp-table-1 {

		compatible = "operating-points-v2";

		opp-shared;
@@ -2276,7 +2276,8 @@ sdhi0: mmc@ee100000 { 
				     "renesas,rcar-gen3-sdhi";

			reg = <0 0xee100000 0 0x2000>;

			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 314>;

			clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774A1_CLK_SD0H>;

			clock-names = "core", "clkh";

			max-frequency = <200000000>;

			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;

			resets = <&cpg 314>;
@@ -2288,7 +2289,8 @@ sdhi1: mmc@ee120000 { 
				     "renesas,rcar-gen3-sdhi";

			reg = <0 0xee120000 0 0x2000>;

			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 313>;

			clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774A1_CLK_SD1H>;

			clock-names = "core", "clkh";

			max-frequency = <200000000>;

			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;

			resets = <&cpg 313>;
@@ -2300,7 +2302,8 @@ sdhi2: mmc@ee140000 { 
				     "renesas,rcar-gen3-sdhi";

			reg = <0 0xee140000 0 0x2000>;

			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 312>;

			clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A774A1_CLK_SD2H>;

			clock-names = "core", "clkh";

			max-frequency = <200000000>;

			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;

			resets = <&cpg 312>;
@@ -2312,7 +2315,8 @@ sdhi3: mmc@ee160000 { 
				     "renesas,rcar-gen3-sdhi";

			reg = <0 0xee160000 0 0x2000>;

			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 311>;

			clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774A1_CLK_SD3H>;

			clock-names = "core", "clkh";

			max-frequency = <200000000>;

			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;

			resets = <&cpg 311>;

arch/arm64/boot/dts/renesas/r8a774b1.dtsi

+9 −5
Original line number Diff line number Diff line
@@ -47,7 +47,7 @@ can_clk: can { 
		clock-frequency = <0>;

	};



	cluster0_opp: opp_table0 {

	cluster0_opp: opp-table-0 {

		compatible = "operating-points-v2";

		opp-shared;
@@ -2133,7 +2133,8 @@ sdhi0: mmc@ee100000 { 
				     "renesas,rcar-gen3-sdhi";

			reg = <0 0xee100000 0 0x2000>;

			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 314>;

			clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774B1_CLK_SD0H>;

			clock-names = "core", "clkh";

			max-frequency = <200000000>;

			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;

			resets = <&cpg 314>;
@@ -2145,7 +2146,8 @@ sdhi1: mmc@ee120000 { 
				     "renesas,rcar-gen3-sdhi";

			reg = <0 0xee120000 0 0x2000>;

			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 313>;

			clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774B1_CLK_SD1H>;

			clock-names = "core", "clkh";

			max-frequency = <200000000>;

			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;

			resets = <&cpg 313>;
@@ -2157,7 +2159,8 @@ sdhi2: mmc@ee140000 { 
				     "renesas,rcar-gen3-sdhi";

			reg = <0 0xee140000 0 0x2000>;

			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 312>;

			clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A774B1_CLK_SD2H>;

			clock-names = "core", "clkh";

			max-frequency = <200000000>;

			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;

			resets = <&cpg 312>;
@@ -2169,7 +2172,8 @@ sdhi3: mmc@ee160000 { 
				     "renesas,rcar-gen3-sdhi";

			reg = <0 0xee160000 0 0x2000>;

			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 311>;

			clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774B1_CLK_SD3H>;

			clock-names = "core", "clkh";

			max-frequency = <200000000>;

			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;

			resets = <&cpg 311>;