Commit 7cf4cc3e authored Dec 02, 2021 by Herve Codina Committed by Arnd Bergmann Dec 13, 2021

ARM: dts: spear3xx: Add spear320s dtsi



The SPEAr320s SOC is a SPEAr320 SOC variant.

Mostly identical to the SPEAr320 SOC variant, it has a
new interrupt routing for PL_PGIOs.

Add spear320s.dtsi to handle SPEAr320s SOC

Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Link: https://lore.kernel.org/r/20211202095255.165797-7-herve.codina@bootlin.com

'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

parent 5d7248e9

arch/arm/boot/dts/spear320s.dtsi

0 → 100644

+24 −0

Original line number	Diff line number	Diff line
		// SPDX-License-Identifier: GPL-2.0-or-later
		/*
		* DTS file for SPEAr320s SoC
		*
		* Copyright 2021 Herve Codina <herve.codina@bootlin.com>
		*/

		/include/ "spear320.dtsi"

		/ {
		ahb {
		apb {
		gpiopinctrl: gpio@b3000000 {
		/*
		* The "RM0321 SPEAr320s address and map
		* registers" document mentions interrupt 6
		* (NPGIO_INTR) for the PL_GPIO interrupt.
		*/
		interrupts = <6>;
		interrupt-parent = <&shirq>;
		};
		};
		};
		};