Commit eca6ab6e authored by Wolfram Sang's avatar Wolfram Sang Committed by Geert Uytterhoeven
Browse files

arm64: dts: reneas: rcar-gen3: Add SDnH clocks 



Signed-off-by: default avatarWolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20211110191610.5664-13-wsa+renesas@sang-engineering.com
Link: https://lore.kernel.org/r/20211110191610.5664-14-wsa+renesas@sang-engineering.com
Link: https://lore.kernel.org/r/20211110191610.5664-15-wsa+renesas@sang-engineering.com
Link: https://lore.kernel.org/r/20211110191610.5664-16-wsa+renesas@sang-engineering.com
Link: https://lore.kernel.org/r/20211110191610.5664-17-wsa+renesas@sang-engineering.com
Link: https://lore.kernel.org/r/20211110191610.5664-18-wsa+renesas@sang-engineering.com
Link: https://lore.kernel.org/r/20211110191610.5664-19-wsa+renesas@sang-engineering.com
Link: https://lore.kernel.org/r/20211110191610.5664-22-wsa+renesas@sang-engineering.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 52e844ee

arch/arm64/boot/dts/renesas/r8a77951.dtsi

+8 −4
Original line number Diff line number Diff line
@@ -2668,7 +2668,8 @@ sdhi0: mmc@ee100000 { 
				     "renesas,rcar-gen3-sdhi";

			reg = <0 0xee100000 0 0x2000>;

			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 314>;

			clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A7795_CLK_SD0H>;

			clock-names = "core", "clkh";

			max-frequency = <200000000>;

			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;

			resets = <&cpg 314>;
@@ -2681,7 +2682,8 @@ sdhi1: mmc@ee120000 { 
				     "renesas,rcar-gen3-sdhi";

			reg = <0 0xee120000 0 0x2000>;

			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 313>;

			clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A7795_CLK_SD1H>;

			clock-names = "core", "clkh";

			max-frequency = <200000000>;

			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;

			resets = <&cpg 313>;
@@ -2694,7 +2696,8 @@ sdhi2: mmc@ee140000 { 
				     "renesas,rcar-gen3-sdhi";

			reg = <0 0xee140000 0 0x2000>;

			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 312>;

			clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A7795_CLK_SD2H>;

			clock-names = "core", "clkh";

			max-frequency = <200000000>;

			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;

			resets = <&cpg 312>;
@@ -2707,7 +2710,8 @@ sdhi3: mmc@ee160000 { 
				     "renesas,rcar-gen3-sdhi";

			reg = <0 0xee160000 0 0x2000>;

			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 311>;

			clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A7795_CLK_SD3H>;

			clock-names = "core", "clkh";

			max-frequency = <200000000>;

			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;

			resets = <&cpg 311>;

arch/arm64/boot/dts/renesas/r8a77960.dtsi

+8 −4
Original line number Diff line number Diff line
@@ -2468,7 +2468,8 @@ sdhi0: mmc@ee100000 { 
				     "renesas,rcar-gen3-sdhi";

			reg = <0 0xee100000 0 0x2000>;

			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 314>;

			clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A7796_CLK_SD0H>;

			clock-names = "core", "clkh";

			max-frequency = <200000000>;

			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;

			resets = <&cpg 314>;
@@ -2481,7 +2482,8 @@ sdhi1: mmc@ee120000 { 
				     "renesas,rcar-gen3-sdhi";

			reg = <0 0xee120000 0 0x2000>;

			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 313>;

			clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A7796_CLK_SD1H>;

			clock-names = "core", "clkh";

			max-frequency = <200000000>;

			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;

			resets = <&cpg 313>;
@@ -2494,7 +2496,8 @@ sdhi2: mmc@ee140000 { 
				     "renesas,rcar-gen3-sdhi";

			reg = <0 0xee140000 0 0x2000>;

			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 312>;

			clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A7796_CLK_SD2H>;

			clock-names = "core", "clkh";

			max-frequency = <200000000>;

			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;

			resets = <&cpg 312>;
@@ -2507,7 +2510,8 @@ sdhi3: mmc@ee160000 { 
				     "renesas,rcar-gen3-sdhi";

			reg = <0 0xee160000 0 0x2000>;

			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 311>;

			clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A7796_CLK_SD3H>;

			clock-names = "core", "clkh";

			max-frequency = <200000000>;

			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;

			resets = <&cpg 311>;

arch/arm64/boot/dts/renesas/r8a77961.dtsi

+8 −4
Original line number Diff line number Diff line
@@ -2312,7 +2312,8 @@ sdhi0: mmc@ee100000 { 
				     "renesas,rcar-gen3-sdhi";

			reg = <0 0xee100000 0 0x2000>;

			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 314>;

			clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A77961_CLK_SD0H>;

			clock-names = "core", "clkh";

			max-frequency = <200000000>;

			power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;

			resets = <&cpg 314>;
@@ -2325,7 +2326,8 @@ sdhi1: mmc@ee120000 { 
				     "renesas,rcar-gen3-sdhi";

			reg = <0 0xee120000 0 0x2000>;

			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 313>;

			clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A77961_CLK_SD1H>;

			clock-names = "core", "clkh";

			max-frequency = <200000000>;

			power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;

			resets = <&cpg 313>;
@@ -2338,7 +2340,8 @@ sdhi2: mmc@ee140000 { 
				     "renesas,rcar-gen3-sdhi";

			reg = <0 0xee140000 0 0x2000>;

			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 312>;

			clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A77961_CLK_SD2H>;

			clock-names = "core", "clkh";

			max-frequency = <200000000>;

			power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;

			resets = <&cpg 312>;
@@ -2351,7 +2354,8 @@ sdhi3: mmc@ee160000 { 
				     "renesas,rcar-gen3-sdhi";

			reg = <0 0xee160000 0 0x2000>;

			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 311>;

			clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A77961_CLK_SD3H>;

			clock-names = "core", "clkh";

			max-frequency = <200000000>;

			power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;

			resets = <&cpg 311>;

arch/arm64/boot/dts/renesas/r8a77965.dtsi

+8 −4
Original line number Diff line number Diff line
@@ -2315,7 +2315,8 @@ sdhi0: mmc@ee100000 { 
				     "renesas,rcar-gen3-sdhi";

			reg = <0 0xee100000 0 0x2000>;

			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 314>;

			clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A77965_CLK_SD0H>;

			clock-names = "core", "clkh";

			max-frequency = <200000000>;

			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;

			resets = <&cpg 314>;
@@ -2328,7 +2329,8 @@ sdhi1: mmc@ee120000 { 
				     "renesas,rcar-gen3-sdhi";

			reg = <0 0xee120000 0 0x2000>;

			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 313>;

			clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A77965_CLK_SD1H>;

			clock-names = "core", "clkh";

			max-frequency = <200000000>;

			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;

			resets = <&cpg 313>;
@@ -2341,7 +2343,8 @@ sdhi2: mmc@ee140000 { 
				     "renesas,rcar-gen3-sdhi";

			reg = <0 0xee140000 0 0x2000>;

			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 312>;

			clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A77965_CLK_SD2H>;

			clock-names = "core", "clkh";

			max-frequency = <200000000>;

			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;

			resets = <&cpg 312>;
@@ -2354,7 +2357,8 @@ sdhi3: mmc@ee160000 { 
				     "renesas,rcar-gen3-sdhi";

			reg = <0 0xee160000 0 0x2000>;

			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 311>;

			clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A77965_CLK_SD3H>;

			clock-names = "core", "clkh";

			max-frequency = <200000000>;

			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;

			resets = <&cpg 311>;

arch/arm64/boot/dts/renesas/r8a77980.dtsi

+2 −1
Original line number Diff line number Diff line
@@ -1339,7 +1339,8 @@ mmc0: mmc@ee140000 { 
				     "renesas,rcar-gen3-sdhi";

			reg = <0 0xee140000 0 0x2000>;

			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 314>;

			clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A77980_CLK_SD0H>;

			clock-names = "core", "clkh";

			power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;

			resets = <&cpg 314>;

			max-frequency = <200000000>;