Commit e5e225fd authored by Zhen Lei's avatar Zhen Lei Committed by Wei Xu
Browse files

ARM: dts: hisilicon: fix errors detected by pl011.yaml 



1. Change node name to match '^serial(@[0-9a-f,]+)*$'
2. Change clock-names to "uartclk", "apb_pclk". Both of them use the same
   clock.
3. Change pinctrl-names to "default", "sleep".

Signed-off-by: default avatarZhen Lei <thunder.leizhen@huawei.com>
Signed-off-by: default avatarWei Xu <xuwei5@hisilicon.com>
parent 30ea026e

arch/arm/boot/dts/hi3519.dtsi

+10 −10
Original line number Diff line number Diff line
@@ -52,8 +52,8 @@ uart0: serial@12100000 { 
			compatible = "arm,pl011", "arm,primecell";

			reg = <0x12100000 0x1000>;

			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&crg HI3519_UART0_CLK>;

			clock-names = "apb_pclk";

			clocks = <&crg HI3519_UART0_CLK>, <&crg HI3519_UART0_CLK>;

			clock-names = "uartclk", "apb_pclk";

			status = "disable";

		};
@@ -61,8 +61,8 @@ uart1: serial@12101000 { 
			compatible = "arm,pl011", "arm,primecell";

			reg = <0x12101000 0x1000>;

			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&crg HI3519_UART1_CLK>;

			clock-names = "apb_pclk";

			clocks = <&crg HI3519_UART1_CLK>, <&crg HI3519_UART1_CLK>;

			clock-names = "uartclk", "apb_pclk";

			status = "disable";

		};
@@ -70,8 +70,8 @@ uart2: serial@12102000 { 
			compatible = "arm,pl011", "arm,primecell";

			reg = <0x12102000 0x1000>;

			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&crg HI3519_UART2_CLK>;

			clock-names = "apb_pclk";

			clocks = <&crg HI3519_UART2_CLK>, <&crg HI3519_UART2_CLK>;

			clock-names = "uartclk", "apb_pclk";

			status = "disable";

		};
@@ -79,8 +79,8 @@ uart3: serial@12103000 { 
			compatible = "arm,pl011", "arm,primecell";

			reg = <0x12103000 0x1000>;

			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&crg HI3519_UART3_CLK>;

			clock-names = "apb_pclk";

			clocks = <&crg HI3519_UART3_CLK>, <&crg HI3519_UART3_CLK>;

			clock-names = "uartclk", "apb_pclk";

			status = "disable";

		};
@@ -88,8 +88,8 @@ uart4: serial@12104000 { 
			compatible = "arm,pl011", "arm,primecell";

			reg = <0x12104000 0x1000>;

			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&crg HI3519_UART4_CLK>;

			clock-names = "apb_pclk";

			clocks = <&crg HI3519_UART4_CLK>, <&crg HI3519_UART4_CLK>;

			clock-names = "uartclk", "apb_pclk";

			status = "disable";

		};

arch/arm/boot/dts/hi3620-hi4511.dts

+10 −10
Original line number Diff line number Diff line
@@ -27,36 +27,36 @@ dual_timer0: dual_timer@800000 { 
			status = "ok";

		};



		uart0: uart@b00000 {	/* console */

			pinctrl-names = "default", "idle";

		uart0: serial@b00000 {	/* console */

			pinctrl-names = "default", "sleep";

			pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>;

			pinctrl-1 = <&uart0_pmx_idle &uart0_cfg_idle>;

			status = "ok";

		};



		uart1: uart@b01000 { /* modem */

			pinctrl-names = "default", "idle";

		uart1: serial@b01000 { /* modem */

			pinctrl-names = "default", "sleep";

			pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>;

			pinctrl-1 = <&uart1_pmx_idle &uart1_cfg_idle>;

			status = "ok";

		};



		uart2: uart@b02000 { /* audience */

			pinctrl-names = "default", "idle";

		uart2: serial@b02000 { /* audience */

			pinctrl-names = "default", "sleep";

			pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;

			pinctrl-1 = <&uart2_pmx_idle &uart2_cfg_idle>;

			status = "ok";

		};



		uart3: uart@b03000 {

			pinctrl-names = "default", "idle";

		uart3: serial@b03000 {

			pinctrl-names = "default", "sleep";

			pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;

			pinctrl-1 = <&uart3_pmx_idle &uart3_cfg_idle>;

			status = "ok";

		};



		uart4: uart@b04000 {

			pinctrl-names = "default", "idle";

		uart4: serial@b04000 {

			pinctrl-names = "default", "sleep";

			pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;

			pinctrl-1 = <&uart4_pmx_idle &uart4_cfg_func>;

			status = "ok";

arch/arm/boot/dts/hi3620.dtsi

+15 −15
Original line number Diff line number Diff line
@@ -172,48 +172,48 @@ timer5: timer@600 { 
			interrupts = <1 13 0xf01>;

		};



		uart0: uart@b00000 {

		uart0: serial@b00000 {

			compatible = "arm,pl011", "arm,primecell";

			reg = <0xb00000 0x1000>;

			interrupts = <0 20 4>;

			clocks = <&clock HI3620_UARTCLK0>;

			clock-names = "apb_pclk";

			clocks = <&clock HI3620_UARTCLK0>, <&clock HI3620_UARTCLK0>;

			clock-names = "uartclk", "apb_pclk";

			status = "disabled";

		};



		uart1: uart@b01000 {

		uart1: serial@b01000 {

			compatible = "arm,pl011", "arm,primecell";

			reg = <0xb01000 0x1000>;

			interrupts = <0 21 4>;

			clocks = <&clock HI3620_UARTCLK1>;

			clock-names = "apb_pclk";

			clocks = <&clock HI3620_UARTCLK1>, <&clock HI3620_UARTCLK1>;

			clock-names = "uartclk", "apb_pclk";

			status = "disabled";

		};



		uart2: uart@b02000 {

		uart2: serial@b02000 {

			compatible = "arm,pl011", "arm,primecell";

			reg = <0xb02000 0x1000>;

			interrupts = <0 22 4>;

			clocks = <&clock HI3620_UARTCLK2>;

			clock-names = "apb_pclk";

			clocks = <&clock HI3620_UARTCLK2>, <&clock HI3620_UARTCLK2>;

			clock-names = "uartclk", "apb_pclk";

			status = "disabled";

		};



		uart3: uart@b03000 {

		uart3: serial@b03000 {

			compatible = "arm,pl011", "arm,primecell";

			reg = <0xb03000 0x1000>;

			interrupts = <0 23 4>;

			clocks = <&clock HI3620_UARTCLK3>;

			clock-names = "apb_pclk";

			clocks = <&clock HI3620_UARTCLK3>, <&clock HI3620_UARTCLK3>;

			clock-names = "uartclk", "apb_pclk";

			status = "disabled";

		};



		uart4: uart@b04000 {

		uart4: serial@b04000 {

			compatible = "arm,pl011", "arm,primecell";

			reg = <0xb04000 0x1000>;

			interrupts = <0 24 4>;

			clocks = <&clock HI3620_UARTCLK4>;

			clock-names = "apb_pclk";

			clocks = <&clock HI3620_UARTCLK4>, <&clock HI3620_UARTCLK4>;

			clock-names = "uartclk", "apb_pclk";

			status = "disabled";

		};

arch/arm/boot/dts/hisi-x5hd2.dtsi

+15 −15
Original line number Diff line number Diff line
@@ -86,48 +86,48 @@ timer4: timer@a81000 { 
				status = "disabled";

			};



			uart0: uart@b00000 {

			uart0: serial@b00000 {

				compatible = "arm,pl011", "arm,primecell";

				reg = <0x00b00000 0x1000>;

				interrupts = <0 49 4>;

				clocks = <&clock HIX5HD2_FIXED_83M>;

				clock-names = "apb_pclk";

				clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>;

				clock-names = "uartclk", "apb_pclk";

				status = "disabled";

			};



			uart1: uart@6000 {

			uart1: serial@6000 {

				compatible = "arm,pl011", "arm,primecell";

				reg = <0x00006000 0x1000>;

				interrupts = <0 50 4>;

				clocks = <&clock HIX5HD2_FIXED_83M>;

				clock-names = "apb_pclk";

				clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>;

				clock-names = "uartclk", "apb_pclk";

				status = "disabled";

			};



			uart2: uart@b02000 {

			uart2: serial@b02000 {

				compatible = "arm,pl011", "arm,primecell";

				reg = <0x00b02000 0x1000>;

				interrupts = <0 51 4>;

				clocks = <&clock HIX5HD2_FIXED_83M>;

				clock-names = "apb_pclk";

				clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>;

				clock-names = "uartclk", "apb_pclk";

				status = "disabled";

			};



			uart3: uart@b03000 {

			uart3: serial@b03000 {

				compatible = "arm,pl011", "arm,primecell";

				reg = <0x00b03000 0x1000>;

				interrupts = <0 52 4>;

				clocks = <&clock HIX5HD2_FIXED_83M>;

				clock-names = "apb_pclk";

				clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>;

				clock-names = "uartclk", "apb_pclk";

				status = "disabled";

			};



			uart4: uart@b04000 {

			uart4: serial@b04000 {

				compatible = "arm,pl011", "arm,primecell";

				reg = <0xb04000 0x1000>;

				interrupts = <0 53 4>;

				clocks = <&clock HIX5HD2_FIXED_83M>;

				clock-names = "apb_pclk";

				clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>;

				clock-names = "uartclk", "apb_pclk";

				status = "disabled";

			};