Commit 30ea026e authored by Zhen Lei's avatar Zhen Lei Committed by Wei Xu
Browse files

ARM: dts: hisilicon: fix errors detected by snps-dw-apb-uart.yaml 



1. Change node name to match '^serial(@[0-9a-f,]+)*$'
2. Change clock-names to "baudclk", "apb_pclk". Both of them use the same
   clock.

Signed-off-by: default avatarZhen Lei <thunder.leizhen@huawei.com>
Signed-off-by: default avatarWei Xu <xuwei5@hisilicon.com>
parent 3650b228

arch/arm/boot/dts/hip01.dtsi

+12 −12
Original line number Diff line number Diff line
@@ -41,41 +41,41 @@ amba { 
			compatible = "simple-bus";

			ranges;



			uart0: uart@10001000 {

			uart0: serial@10001000 {

				compatible = "snps,dw-apb-uart";

				reg = <0x10001000 0x1000>;

				clocks = <&hisi_refclk144mhz>;

				clock-names = "apb_pclk";

				clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>;

				clock-names = "baudclk", "apb_pclk";

				reg-shift = <2>;

				interrupts = <0 32 4>;

				status = "disabled";

			};



			uart1: uart@10002000 {

			uart1: serial@10002000 {

				compatible = "snps,dw-apb-uart";

				reg = <0x10002000 0x1000>;

				clocks = <&hisi_refclk144mhz>;

				clock-names = "apb_pclk";

				clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>;

				clock-names = "baudclk", "apb_pclk";

				reg-shift = <2>;

				interrupts = <0 33 4>;

				status = "disabled";

			};



			uart2: uart@10003000 {

			uart2: serial@10003000 {

				compatible = "snps,dw-apb-uart";

				reg = <0x10003000 0x1000>;

				clocks = <&hisi_refclk144mhz>;

				clock-names = "apb_pclk";

				clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>;

				clock-names = "baudclk", "apb_pclk";

				reg-shift = <2>;

				interrupts = <0 34 4>;

				status = "disabled";

			};



			uart3: uart@10006000 {

			uart3: serial@10006000 {

				compatible = "snps,dw-apb-uart";

				reg = <0x10006000 0x1000>;

				clocks = <&hisi_refclk144mhz>;

				clock-names = "apb_pclk";

				clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>;

				clock-names = "baudclk", "apb_pclk";

				reg-shift = <2>;

				interrupts = <0 4 4>;

				status = "disabled";

arch/arm/boot/dts/hip04-d01.dts

+1 −1
Original line number Diff line number Diff line
@@ -22,7 +22,7 @@ memory@0,10000000 { 
	};



	soc {

		uart0: uart@4007000 {

		uart0: serial@4007000 {

			status = "ok";

		};

	};

arch/arm/boot/dts/hip04.dtsi

+3 −3
Original line number Diff line number Diff line
@@ -250,12 +250,12 @@ arm-pmu { 
				     <0 79 4>;

		};



		uart0: uart@4007000 {

		uart0: serial@4007000 {

			compatible = "snps,dw-apb-uart";

			reg = <0x4007000 0x1000>;

			interrupts = <0 381 4>;

			clocks = <&clk_168m>;

			clock-names = "uartclk";

			clocks = <&clk_168m>, <&clk_168m>;

			clock-names = "baudclk", "apb_pclk";

			reg-shift = <2>;

			status = "disabled";

		};