clk: renesas: r9a09g011: Add PFC clock and reset entries

Add PFC clock/reset entries to CPG driver.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220518135208.39885-1-phil.edworthy@renesas.com


Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>