Commit df81b941 authored by Linus Walleij's avatar Linus Walleij
Browse files

Merge tag 'sh-pfc-for-v4.13-tag2' of... 

Merge tag 'sh-pfc-for-v4.13-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: sh-pfc: Updates for v4.13 (take two)

  - Add SCIF1 and SCIF2 pin groups for R-Car V2H,
  - Add EtherAVB, DU parallel RGB output, and PWM pin groups for R-Car
    H3 ES2.0,
  - Add pin and gpio controller support for RZ/A1.
parents b3060044 c03a133b

Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt

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Renesas RZ/A1 combined Pin and GPIO controller



The Renesas SoCs of the RZ/A1 family feature a combined Pin and GPIO controller,

named "Ports" in the hardware reference manual.

Pin multiplexing and GPIO configuration is performed on a per-pin basis

writing configuration values to per-port register sets.

Each "port" features up to 16 pins, each of them configurable for GPIO

function (port mode) or in alternate function mode.

Up to 8 different alternate function modes exist for each single pin.



Pin controller node

-------------------



Required properties:

  - compatible

    this shall be "renesas,r7s72100-ports".



  - reg

    address base and length of the memory area where the pin controller

    hardware is mapped to.



Example:

Pin controller node for RZ/A1H SoC (r7s72100)



pinctrl: pin-controller@fcfe3000 {

	compatible = "renesas,r7s72100-ports";



	reg = <0xfcfe3000 0x4230>;

};



Sub-nodes

---------



The child nodes of the pin controller node describe a pin multiplexing

function or a GPIO controller alternatively.



- Pin multiplexing sub-nodes:

  A pin multiplexing sub-node describes how to configure a set of

  (or a single) pin in some desired alternate function mode.

  A single sub-node may define several pin configurations.

  A few alternate function require special pin configuration flags to be

  supplied along with the alternate function configuration number.

  The hardware reference manual specifies when a pin function requires

  "software IO driven" mode to be specified. To do so use the generic

  properties from the <include/linux/pinctrl/pinconf_generic.h> header file

  to instruct the pin controller to perform the desired pin configuration

  operation.

  Please refer to pinctrl-bindings.txt to get to know more on generic

  pin properties usage.



  The allowed generic formats for a pin multiplexing sub-node are the

  following ones:



  node-1 {

      pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;

      GENERIC_PINCONFIG;

  };



  node-2 {

      sub-node-1 {

          pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;

          GENERIC_PINCONFIG;

      };



      sub-node-2 {

          pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;

          GENERIC_PINCONFIG;

      };



      ...



      sub-node-n {

          pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;

          GENERIC_PINCONFIG;

      };

  };



  Use the second format when pins part of the same logical group need to have

  different generic pin configuration flags applied.



  Client sub-nodes shall refer to pin multiplexing sub-nodes using the phandle

  of the most external one.



  Eg.



  client-1 {

      ...

      pinctrl-0 = <&node-1>;

      ...

  };



  client-2 {

      ...

      pinctrl-0 = <&node-2>;

      ...

  };



  Required properties:

    - pinmux:

      integer array representing pin number and pin multiplexing configuration.

      When a pin has to be configured in alternate function mode, use this

      property to identify the pin by its global index, and provide its

      alternate function configuration number along with it.

      When multiple pins are required to be configured as part of the same

      alternate function they shall be specified as members of the same

      argument list of a single "pinmux" property.

      Helper macros to ease assembling the pin index from its position

      (port where it sits on and pin number) and alternate function identifier

      are provided by the pin controller header file at:

      <include/dt-bindings/pinctrl/r7s72100-pinctrl.h>

      Integers values in "pinmux" argument list are assembled as:

      ((PORT * 16 + PIN) | MUX_FUNC << 16)



  Optional generic properties:

    - input-enable:

      enable input bufer for pins requiring software driven IO input

      operations.

    - output-high:

      enable output buffer for pins requiring software driven IO output

      operations. output-low can be used alternatively, as line value is

      ignored by the driver.



  The hardware reference manual specifies when a pin has to be configured to

  work in bi-directional mode and when the IO direction has to be specified

  by software. Bi-directional pins are managed by the pin controller driver

  internally, while software driven IO direction has to be explicitly

  selected when multiple options are available.



  Example:

  A serial communication interface with a TX output pin and an RX input pin.



  &pinctrl {

	scif2_pins: serial2 {

		pinmux = <RZA1_PINMUX(3, 0, 6)>, <RZA1_PINMUX(3, 2, 4)>;

	};

  };



  Pin #0 on port #3 is configured as alternate function #6.

  Pin #2 on port #3 is configured as alternate function #4.



  Example 2:

  I2c master: both SDA and SCL pins need bi-directional operations



  &pinctrl {

	i2c2_pins: i2c2 {

		pinmux = <RZA1_PINMUX(1, 4, 1)>, <RZA1_PINMUX(1, 5, 1)>;

	};

  };



  Pin #4 on port #1 is configured as alternate function #1.

  Pin #5 on port #1 is configured as alternate function #1.

  Both need to work in bi-directional mode, the driver manages this internally.



  Example 3:

  Multi-function timer input and output compare pins.

  Configure TIOC0A as software driven input and TIOC0B as software driven

  output.



  &pinctrl {

	tioc0_pins: tioc0 {

		tioc0_input_pins {

			pinumx = <RZA1_PINMUX(4, 0, 2)>;

			input-enable;

		};



		tioc0_output_pins {

			pinmux = <RZA1_PINMUX(4, 1, 1)>;

			output-enable;

		};

	};

  };



  &tioc0 {

	...

	pinctrl-0 = <&tioc0_pins>;

	...

  };



  Pin #0 on port #4 is configured as alternate function #2 with IO direction

  specified by software as input.

  Pin #1 on port #4 is configured as alternate function #1 with IO direction

  specified by software as output.



- GPIO controller sub-nodes:

  Each port of the r7s72100 pin controller hardware is itself a GPIO controller.

  Different SoCs have different numbers of available pins per port, but

  generally speaking, each of them can be configured in GPIO ("port") mode

  on this hardware.

  Describe GPIO controllers using sub-nodes with the following properties.



  Required properties:

    - gpio-controller

      empty property as defined by the GPIO bindings documentation.

    - #gpio-cells

      number of cells required to identify and configure a GPIO.

      Shall be 2.

    - gpio-ranges

      Describes a GPIO controller specifying its specific pin base, the pin

      base in the global pin numbering space, and the number of controlled

      pins, as defined by the GPIO bindings documentation. Refer to

      Documentation/devicetree/bindings/gpio/gpio.txt file for a more detailed

      description.



  Example:

  A GPIO controller node, controlling 16 pins indexed from 0.

  The GPIO controller base in the global pin indexing space is pin 48, thus

  pins [0 - 15] on this controller map to pins [48 - 63] in the global pin

  indexing space.



  port3: gpio-3 {

	gpio-controller;

	#gpio-cells = <2>;

	gpio-ranges = <&pinctrl 0 48 16>;

  };



  A device node willing to use pins controlled by this GPIO controller, shall

  refer to it as follows:



  led1 {

	gpios = <&port3 10 GPIO_ACTIVE_LOW>;

  };

drivers/pinctrl/Kconfig

+11 −0
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@@ -188,6 +188,17 @@ config PINCTRL_ROCKCHIP 
	select GENERIC_IRQ_CHIP

	select MFD_SYSCON



config PINCTRL_RZA1

	bool "Renesas RZ/A1 gpio and pinctrl driver"

	depends on OF

	depends on ARCH_R7S72100 || COMPILE_TEST

	select GPIOLIB

	select GENERIC_PINCTRL_GROUPS

	select GENERIC_PINMUX_FUNCTIONS

	select GENERIC_PINCONF

	help

	  This selects pinctrl driver for Renesas RZ/A1 platforms.



config PINCTRL_SINGLE

	tristate "One-register-per-pin type device tree based pinctrl driver"

	depends on OF

drivers/pinctrl/Makefile

+1 −0
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@@ -26,6 +26,7 @@ obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o 
obj-$(CONFIG_PINCTRL_PIC32)	+= pinctrl-pic32.o

obj-$(CONFIG_PINCTRL_PISTACHIO)	+= pinctrl-pistachio.o

obj-$(CONFIG_PINCTRL_ROCKCHIP)	+= pinctrl-rockchip.o

obj-$(CONFIG_PINCTRL_RZA1)	+= pinctrl-rza1.o

obj-$(CONFIG_PINCTRL_SINGLE)	+= pinctrl-single.o

obj-$(CONFIG_PINCTRL_SIRF)	+= sirf/

obj-$(CONFIG_PINCTRL_SX150X)	+= pinctrl-sx150x.o

drivers/pinctrl/pinctrl-rza1.c

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+1311 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/pinctrl/sh-pfc/pfc-r8a7792.c

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@@ -1137,6 +1137,43 @@ static const unsigned int scif0_ctrl_pins[] = { 
static const unsigned int scif0_ctrl_mux[] = {

	RTS0_N_MARK, CTS0_N_MARK,

};

/* - SCIF1 ------------------------------------------------------------------ */

static const unsigned int scif1_data_pins[] = {

	/* RX, TX */

	RCAR_GP_PIN(10, 19), RCAR_GP_PIN(10, 18),

};

static const unsigned int scif1_data_mux[] = {

	RX1_MARK, TX1_MARK,

};

static const unsigned int scif1_clk_pins[] = {

	/* SCK */

	RCAR_GP_PIN(10, 15),

};

static const unsigned int scif1_clk_mux[] = {

	SCK1_MARK,

};

static const unsigned int scif1_ctrl_pins[] = {

	/* RTS, CTS */

	RCAR_GP_PIN(10, 17), RCAR_GP_PIN(10, 16),

};

static const unsigned int scif1_ctrl_mux[] = {

	RTS1_N_MARK, CTS1_N_MARK,

};

/* - SCIF2 ------------------------------------------------------------------ */

static const unsigned int scif2_data_pins[] = {

	/* RX, TX */

	RCAR_GP_PIN(10, 22), RCAR_GP_PIN(10, 21),

};

static const unsigned int scif2_data_mux[] = {

	RX2_MARK, TX2_MARK,

};

static const unsigned int scif2_clk_pins[] = {

	/* SCK */

	RCAR_GP_PIN(10, 20),

};

static const unsigned int scif2_clk_mux[] = {

	SCK2_MARK,

};

/* - SCIF3 ------------------------------------------------------------------ */

static const unsigned int scif3_data_pins[] = {

	/* RX, TX */
@@ -1680,6 +1717,11 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { 
	SH_PFC_PIN_GROUP(scif0_data),

	SH_PFC_PIN_GROUP(scif0_clk),

	SH_PFC_PIN_GROUP(scif0_ctrl),

	SH_PFC_PIN_GROUP(scif1_data),

	SH_PFC_PIN_GROUP(scif1_clk),

	SH_PFC_PIN_GROUP(scif1_ctrl),

	SH_PFC_PIN_GROUP(scif2_data),

	SH_PFC_PIN_GROUP(scif2_clk),

	SH_PFC_PIN_GROUP(scif3_data),

	SH_PFC_PIN_GROUP(scif3_clk),

	SH_PFC_PIN_GROUP(sdhi0_data1),
@@ -1826,6 +1868,17 @@ static const char * const scif0_groups[] = { 
	"scif0_ctrl",

};



static const char * const scif1_groups[] = {

	"scif1_data",

	"scif1_clk",

	"scif1_ctrl",

};



static const char * const scif2_groups[] = {

	"scif2_data",

	"scif2_clk",

};



static const char * const scif3_groups[] = {

	"scif3_data",

	"scif3_clk",
@@ -1924,6 +1977,8 @@ static const struct sh_pfc_function pinmux_functions[] = { 
	SH_PFC_FUNCTION(msiof1),

	SH_PFC_FUNCTION(qspi),

	SH_PFC_FUNCTION(scif0),

	SH_PFC_FUNCTION(scif1),

	SH_PFC_FUNCTION(scif2),

	SH_PFC_FUNCTION(scif3),

	SH_PFC_FUNCTION(sdhi0),

	SH_PFC_FUNCTION(vin0),