Commit de395577 authored by Dave Stevenson's avatar Dave Stevenson Committed by Mauro Carvalho Chehab
Browse files

media: i2c: imx290: Support 60fps in 2 lane operation 



Commit "97589ad6 media: i2c: imx290: Add support for 2 data lanes"
added support for running in two lane mode (instead of 4), but
without changing the link frequency that resulted in a max of 30fps.

Commit "98e0500e media: i2c: imx290: Add configurable link frequency
and pixel rate" then doubled the link frequency when in 2 lane mode,
but didn't undo the correction for running at only 30fps, just extending
horizontal blanking instead.

Remove the 30fps limit on 2 lane by correcting the register config
in accordance with the datasheet for 60fps operation over 2 lanes.

Signed-off-by: default avatarDave Stevenson <dave.stevenson@raspberrypi.com>
Reviewed-by: default avatarAlexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: default avatarLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: default avatarSakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@kernel.org>
parent bc35f9a2

drivers/media/i2c/imx290.c

+3 −14
Original line number Diff line number Diff line
@@ -385,7 +385,7 @@ static const struct imx290_mode imx290_modes_2lanes[] = { 
	{

		.width = 1920,

		.height = 1080,

		.hmax = 4400,

		.hmax = 2200,

		.link_freq_index = FREQ_INDEX_1080P,

		.data = imx290_1080p_settings,

		.data_size = ARRAY_SIZE(imx290_1080p_settings),
@@ -393,7 +393,7 @@ static const struct imx290_mode imx290_modes_2lanes[] = { 
	{

		.width = 1280,

		.height = 720,

		.hmax = 6600,

		.hmax = 3300,

		.link_freq_index = FREQ_INDEX_720P,

		.data = imx290_720p_settings,

		.data_size = ARRAY_SIZE(imx290_720p_settings),
@@ -544,21 +544,10 @@ static int imx290_set_register_array(struct imx290 *imx290, 
static int imx290_set_data_lanes(struct imx290 *imx290)

{

	int ret = 0;

	u32 frsel;



	switch (imx290->nlanes) {

	case 2:

	default:

		frsel = 0x02;

		break;

	case 4:

		frsel = 0x01;

		break;

	}



	imx290_write(imx290, IMX290_PHY_LANE_NUM, imx290->nlanes - 1, &ret);

	imx290_write(imx290, IMX290_CSI_LANE_MODE, imx290->nlanes - 1, &ret);

	imx290_write(imx290, IMX290_FR_FDG_SEL, frsel, &ret);

	imx290_write(imx290, IMX290_FR_FDG_SEL, 0x01, &ret);



	return ret;

}