Commit dbb3e2fb authored by Sujith Manoharan's avatar Sujith Manoharan Committed by John W. Linville
Browse files

ath9k: Remove duplicate initvals for AR9462 v2.1 



The initvals for AR9462 v2.1 are very similar to v2.0.
Identify duplicate arrays and reuse the values from v2.0
to reduce module size.

Signed-off-by: default avatarSujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 3777f7d1

drivers/net/wireless/ath/ath9k/ar9003_hw.c

+12 −12
Original line number Diff line number Diff line
@@ -252,18 +252,18 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah) 
				ar9462_2p0_soc_postamble);



		INIT_INI_ARRAY(&ah->iniModesRxGain,

				ar9462_common_rx_gain_table_2p0);

				ar9462_2p0_common_rx_gain);



		/* Awake -> Sleep Setting */

		INIT_INI_ARRAY(&ah->iniPcieSerdes,

			       ar9462_pciephy_clkreq_disable_L1_2p0);

			       ar9462_2p0_pciephy_clkreq_disable_L1);

		/* Sleep -> Awake Setting */

		INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,

			       ar9462_pciephy_clkreq_disable_L1_2p0);

			       ar9462_2p0_pciephy_clkreq_disable_L1);



		/* Fast clock modal settings */

		INIT_INI_ARRAY(&ah->iniModesFastClock,

				ar9462_modes_fast_clock_2p0);

				ar9462_2p0_modes_fast_clock);



		INIT_INI_ARRAY(&ah->iniCckfirJapan2484,

			       ar9462_2p0_baseband_core_txfir_coeff_japan_2484);
@@ -480,7 +480,7 @@ static void ar9003_tx_gain_table_mode0(struct ath_hw *ah) 
			ar9462_2p1_modes_low_ob_db_tx_gain);

	else if (AR_SREV_9462_20(ah))

		INIT_INI_ARRAY(&ah->iniModesTxGain,

			ar9462_modes_low_ob_db_tx_gain_table_2p0);

			ar9462_2p0_modes_low_ob_db_tx_gain);

	else if (AR_SREV_9565_11(ah))

		INIT_INI_ARRAY(&ah->iniModesTxGain,

			       ar9565_1p1_modes_low_ob_db_tx_gain_table);
@@ -517,7 +517,7 @@ static void ar9003_tx_gain_table_mode1(struct ath_hw *ah) 
			ar9462_2p1_modes_high_ob_db_tx_gain);

	else if (AR_SREV_9462_20(ah))

		INIT_INI_ARRAY(&ah->iniModesTxGain,

			ar9462_modes_high_ob_db_tx_gain_table_2p0);

			ar9462_2p0_modes_high_ob_db_tx_gain);

	else if (AR_SREV_9565_11(ah))

		INIT_INI_ARRAY(&ah->iniModesTxGain,

			       ar9565_1p1_modes_high_ob_db_tx_gain_table);
@@ -598,7 +598,7 @@ static void ar9003_tx_gain_table_mode4(struct ath_hw *ah) 
		       ar9462_2p1_modes_mix_ob_db_tx_gain);

	else if (AR_SREV_9462_20(ah))

		INIT_INI_ARRAY(&ah->iniModesTxGain,

		       ar9462_modes_mix_ob_db_tx_gain_table_2p0);

		       ar9462_2p0_modes_mix_ob_db_tx_gain);

	else

		INIT_INI_ARRAY(&ah->iniModesTxGain,

			ar9300Modes_mixed_ob_db_tx_gain_table_2p2);
@@ -689,7 +689,7 @@ static void ar9003_rx_gain_table_mode0(struct ath_hw *ah) 
				ar9462_2p1_common_rx_gain);

	else if (AR_SREV_9462_20(ah))

		INIT_INI_ARRAY(&ah->iniModesRxGain,

				ar9462_common_rx_gain_table_2p0);

				ar9462_2p0_common_rx_gain);

	else if (AR_SREV_9565_11(ah))

		INIT_INI_ARRAY(&ah->iniModesRxGain,

			       ar9565_1p1_Common_rx_gain_table);
@@ -720,7 +720,7 @@ static void ar9003_rx_gain_table_mode1(struct ath_hw *ah) 
			ar9462_2p1_common_wo_xlna_rx_gain);

	else if (AR_SREV_9462_20(ah))

		INIT_INI_ARRAY(&ah->iniModesRxGain,

			ar9462_common_wo_xlna_rx_gain_table_2p0);

			ar9462_2p0_common_wo_xlna_rx_gain);

	else if (AR_SREV_9550(ah)) {

		INIT_INI_ARRAY(&ah->iniModesRxGain,

			ar955x_1p0_common_wo_xlna_rx_gain_table);
@@ -753,7 +753,7 @@ static void ar9003_rx_gain_table_mode2(struct ath_hw *ah) 
			       ar9462_2p1_baseband_postamble_5g_xlna);

	} else if (AR_SREV_9462_20(ah)) {

		INIT_INI_ARRAY(&ah->iniModesRxGain,

			       ar9462_common_mixed_rx_gain_table_2p0);

			       ar9462_2p0_common_mixed_rx_gain);

		INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_core,

			       ar9462_2p0_baseband_core_mix_rxgain);

		INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
@@ -767,12 +767,12 @@ static void ar9003_rx_gain_table_mode3(struct ath_hw *ah) 
{

	if (AR_SREV_9462_21(ah)) {

		INIT_INI_ARRAY(&ah->iniModesRxGain,

			       ar9462_2p1_common_5g_xlna_only_rx_gain);

			       ar9462_2p1_common_5g_xlna_only_rxgain);

		INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna,

			       ar9462_2p1_baseband_postamble_5g_xlna);

	} else if (AR_SREV_9462_20(ah)) {

		INIT_INI_ARRAY(&ah->iniModesRxGain,

			       ar9462_2p0_5g_xlna_only_rxgain);

			       ar9462_2p0_common_5g_xlna_only_rxgain);

		INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna,

			       ar9462_2p0_baseband_postamble_5g_xlna);

	}

drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h

+9 −9
Original line number Diff line number Diff line
@@ -20,7 +20,7 @@ 


/* AR9462 2.0 */



static const u32 ar9462_modes_fast_clock_2p0[][3] = {

static const u32 ar9462_2p0_modes_fast_clock[][3] = {

	/* Addr      5G_HT20     5G_HT40   */

	{0x00001030, 0x00000268, 0x000004d0},

	{0x00001070, 0x0000018c, 0x00000318},
@@ -92,7 +92,7 @@ static const u32 ar9462_2p0_baseband_postamble[][5] = { 
	{0x0000b284, 0x00000000, 0x00000000, 0x00000550, 0x00000550},

};



static const u32 ar9462_common_rx_gain_table_2p0[][2] = {

static const u32 ar9462_2p0_common_rx_gain[][2] = {

	/* Addr      allmodes  */

	{0x0000a000, 0x00010000},

	{0x0000a004, 0x00030002},
@@ -352,7 +352,7 @@ static const u32 ar9462_common_rx_gain_table_2p0[][2] = { 
	{0x0000b1fc, 0x00000196},

};



static const u32 ar9462_pciephy_clkreq_disable_L1_2p0[][2] = {

static const u32 ar9462_2p0_pciephy_clkreq_disable_L1[][2] = {

	/* Addr      allmodes  */

	{0x00018c00, 0x18213ede},

	{0x00018c04, 0x000801d8},
@@ -366,7 +366,7 @@ static const u32 ar9462_2p0_radio_postamble_sys2ant[][5] = { 
	{0x00016540, 0x10804008, 0x10804008, 0x50804008, 0x50804008},

};



static const u32 ar9462_common_wo_xlna_rx_gain_table_2p0[][2] = {

static const u32 ar9462_2p0_common_wo_xlna_rx_gain[][2] = {

	/* Addr      allmodes  */

	{0x0000a000, 0x00010000},

	{0x0000a004, 0x00030002},
@@ -633,7 +633,7 @@ static const u32 ar9462_2p0_baseband_core_txfir_coeff_japan_2484[][2] = { 
	{0x0000a3a0, 0xca9228ee},

};



static const u32 ar9462_modes_low_ob_db_tx_gain_table_2p0[][5] = {

static const u32 ar9462_2p0_modes_low_ob_db_tx_gain[][5] = {

	/* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */

	{0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},

	{0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
@@ -865,7 +865,7 @@ static const u32 ar9462_2p0_radio_postamble[][5] = { 
	{0x0001650c, 0x48000000, 0x40000000, 0x40000000, 0x40000000},

};



static const u32 ar9462_modes_mix_ob_db_tx_gain_table_2p0[][5] = {

static const u32 ar9462_2p0_modes_mix_ob_db_tx_gain[][5] = {

	/* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */

	{0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},

	{0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
@@ -928,7 +928,7 @@ static const u32 ar9462_modes_mix_ob_db_tx_gain_table_2p0[][5] = { 
	{0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},

};



static const u32 ar9462_modes_high_ob_db_tx_gain_table_2p0[][5] = {

static const u32 ar9462_2p0_modes_high_ob_db_tx_gain[][5] = {

	/* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */

	{0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},

	{0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
@@ -1238,7 +1238,7 @@ static const u32 ar9462_2p0_mac_postamble[][5] = { 
	{0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},

};



static const u32 ar9462_common_mixed_rx_gain_table_2p0[][2] = {

static const u32 ar9462_2p0_common_mixed_rx_gain[][2] = {

	/* Addr      allmodes  */

	{0x0000a000, 0x00010000},

	{0x0000a004, 0x00030002},
@@ -1503,7 +1503,7 @@ static const u32 ar9462_2p0_baseband_postamble_5g_xlna[][5] = { 
	{0x00009e3c, 0xcf946220, 0xcf946220, 0xcfd5c782, 0xcfd5c282},

};



static const u32 ar9462_2p0_5g_xlna_only_rxgain[][2] = {

static const u32 ar9462_2p0_common_5g_xlna_only_rxgain[][2] = {

	/* Addr      allmodes  */

	{0x0000a000, 0x00010000},

	{0x0000a004, 0x00030002},

drivers/net/wireless/ath/ath9k/ar9462_2p1_initvals.h

+38 −1528

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h

+1 −1
Original line number Diff line number Diff line
@@ -771,7 +771,7 @@ static const u32 ar9580_1p0_soc_preamble[][2] = { 
	{0x00007048, 0x00000008},

};



#define ar9580_1p0_rx_gain_table ar9462_common_rx_gain_table_2p0

#define ar9580_1p0_rx_gain_table ar9462_2p0_common_rx_gain



static const u32 ar9580_1p0_radio_core[][2] = {

	/* Addr      allmodes  */