Commit d94585a0 authored by Yue Hin Lau's avatar Yue Hin Lau Committed by Alex Deucher
Browse files

drm/amd/display: rename transform to dpp for dcn 



Signed-off-by: default avatarYue Hin Lau <Yuehin.Lau@amd.com>
Reviewed-by: default avatarEric Bernstein <Eric.Bernstein@amd.com>
Acked-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 39a4e660

drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c

+1 −0
Original line number Diff line number Diff line
@@ -488,6 +488,7 @@ static void split_stream_across_pipes( 
	secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];

	secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx];

	secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx];

	secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];

	if (primary_pipe->bottom_pipe) {

		ASSERT(primary_pipe->bottom_pipe != secondary_pipe);

		secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe;

drivers/gpu/drm/amd/display/dc/core/dc.c

+1 −0
Original line number Diff line number Diff line
@@ -38,6 +38,7 @@ 
#include "bios_parser_interface.h"

#include "include/irq_service_interface.h"

#include "transform.h"

#include "dpp.h"

#include "timing_generator.h"

#include "virtual/virtual_link_encoder.h"

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

+13 −3
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@ 
#include "opp.h"

#include "timing_generator.h"

#include "transform.h"

#include "dpp.h"

#include "core_types.h"

#include "set_mode_types.h"

#include "virtual/virtual_stream_encoder.h"
@@ -853,15 +854,23 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) 
	pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable;



	/* Taps calculations */

	if (pipe_ctx->plane_res.xfm != NULL)

		res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(

				pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);



	if (pipe_ctx->plane_res.dpp != NULL)

		res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(

				pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);



	if (!res) {

		/* Try 24 bpp linebuffer */

		pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP;



		res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(

			pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);



		res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(

			pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);

	}



	if (res)
@@ -1026,7 +1035,7 @@ static int acquire_first_split_pipe( 
			pipe_ctx->stream_res.tg = pool->timing_generators[i];

			pipe_ctx->plane_res.hubp = pool->hubps[i];

			pipe_ctx->plane_res.ipp = pool->ipps[i];

			pipe_ctx->plane_res.xfm = pool->transforms[i];

			pipe_ctx->plane_res.dpp = pool->dpps[i];

			pipe_ctx->stream_res.opp = pool->opps[i];

			pipe_ctx->pipe_idx = i;
@@ -1359,6 +1368,7 @@ static int acquire_first_free_pipe( 
			pipe_ctx->plane_res.hubp = pool->hubps[i];

			pipe_ctx->plane_res.ipp = pool->ipps[i];

			pipe_ctx->plane_res.xfm = pool->transforms[i];

			pipe_ctx->plane_res.dpp = pool->dpps[i];

			pipe_ctx->stream_res.opp = pool->opps[i];

			pipe_ctx->pipe_idx = i;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

+13 −3
Original line number Diff line number Diff line
@@ -200,7 +200,7 @@ bool dc_stream_set_cursor_attributes( 
	for (i = 0; i < MAX_PIPES; i++) {

		struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];



		if (pipe_ctx->stream != stream || !pipe_ctx->plane_res.xfm)

		if (pipe_ctx->stream != stream || (!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp))

			continue;

		if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)

			continue;
@@ -221,9 +221,15 @@ bool dc_stream_set_cursor_attributes( 
					pipe_ctx->plane_res.mi, attributes);





		if (pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes != NULL)

		if (pipe_ctx->plane_res.xfm != NULL &&

				pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes != NULL)

			pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes(

				pipe_ctx->plane_res.xfm, attributes);



		if (pipe_ctx->plane_res.dpp != NULL &&

				pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes != NULL)

			pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes(

				pipe_ctx->plane_res.dpp, attributes);

	}



	stream->cursor_attributes = *attributes;
@@ -258,6 +264,7 @@ bool dc_stream_set_cursor_position( 
		struct mem_input *mi = pipe_ctx->plane_res.mi;

		struct hubp *hubp = pipe_ctx->plane_res.hubp;

		struct transform *xfm = pipe_ctx->plane_res.xfm;

		struct dpp *dpp = pipe_ctx->plane_res.dpp;

		struct dc_cursor_position pos_cpy = *position;

		struct dc_cursor_mi_param param = {

			.pixel_clk_khz = stream->timing.pix_clk_khz,
@@ -270,7 +277,7 @@ bool dc_stream_set_cursor_position( 
		if (pipe_ctx->stream != stream ||

				(!pipe_ctx->plane_res.mi  && !pipe_ctx->plane_res.hubp) ||

				!pipe_ctx->plane_state ||

				!pipe_ctx->plane_res.xfm)

				(!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp))

			continue;



		if (pipe_ctx->plane_state->address.type
@@ -293,6 +300,9 @@ bool dc_stream_set_cursor_position( 
		if (xfm != NULL && xfm->funcs->set_cursor_position != NULL)

			xfm->funcs->set_cursor_position(xfm, &pos_cpy, &param, hubp->curs_attr.width);



		if (dpp != NULL && dpp->funcs->set_cursor_position != NULL)

			dpp->funcs->set_cursor_position(dpp, &pos_cpy, &param, hubp->curs_attr.width);



	}



	return true;

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

+1 −0
Original line number Diff line number Diff line
@@ -30,6 +30,7 @@ 
/* DC core (private) */

#include "core_types.h"

#include "transform.h"

#include "dpp.h"



/*******************************************************************************

 * Private functions