Commit d91dfe50 authored by Hou Zhiqiang's avatar Hou Zhiqiang Committed by Bjorn Helgaas
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PCI: dwc: Enable write permission for Class Code, Interrupt Pin updates 



dw_pcie_setup_rc() contains fixes to update the Class Code and Interrupt
Pin registers, but the fixes don't actually work because these registers
are read-only.

Enable write permission before updating the Class Code and Interrupt
Pin.

Signed-off-by: default avatarHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Acked-by: default avatarJoao Pinto <jpinto@synopsys.com>
Acked-by: default avatarRoy Zang <tie-fei.zang@freescale.com>
parent e44abfed

drivers/pci/dwc/pcie-designware-host.c

+6 −0
Original line number Diff line number Diff line
@@ -597,10 +597,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp) 
	dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000);



	/* setup interrupt pins */

	dw_pcie_dbi_ro_wr_en(pci);

	val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE);

	val &= 0xffff00ff;

	val |= 0x00000100;

	dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val);

	dw_pcie_dbi_ro_wr_dis(pci);



	/* setup bus numbers */

	val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS);
@@ -637,8 +639,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp) 


	dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);



	/* Enable write permission for the DBI read-only register */

	dw_pcie_dbi_ro_wr_en(pci);

	/* program correct class for RC */

	dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);

	/* Better disable write permission right after the update */

	dw_pcie_dbi_ro_wr_dis(pci);



	dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);

	val |= PORT_LOGIC_SPEED_CHANGE;