Commit e44abfed authored by Hou Zhiqiang's avatar Hou Zhiqiang Committed by Bjorn Helgaas
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PCI: dwc: Add accessors for write permission of DBI read-only registers 



The read-only DBI registers can be written only when the "Write to RO
Registers Using DBI" (DBI_RO_WR_EN) field of MISC_CONTROL_1_OFF is set.

Add accessors to enable and disable write permission, and use them instead
of accessing MISC_CONTROL_1_OFF directly.

Signed-off-by: default avatarHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Acked-by: default avatarJoao Pinto <jpinto@synopsys.com>
Acked-by: default avatarRoy Zang <tie-fei.zang@freescale.com>
parent 4a2745d7

drivers/pci/dwc/pci-layerscape.c

+2 −3
Original line number Diff line number Diff line
@@ -33,7 +33,6 @@ 


/* PEX Internal Configuration Registers */

#define PCIE_STRFMR1		0x71c /* Symbol Timer & Filter Mask Register1 */

#define PCIE_DBI_RO_WR_EN	0x8bc /* DBI Read-Only Write Enable Register */



#define PCIE_IATU_NUM		6
@@ -145,10 +144,10 @@ static int ls_pcie_host_init(struct pcie_port *pp) 
	 */

	ls_pcie_disable_outbound_atus(pcie);



	iowrite32(1, pci->dbi_base + PCIE_DBI_RO_WR_EN);

	dw_pcie_dbi_ro_wr_en(pci);

	ls_pcie_fix_class(pcie);

	ls_pcie_clear_multifunction(pcie);

	iowrite32(0, pci->dbi_base + PCIE_DBI_RO_WR_EN);

	dw_pcie_dbi_ro_wr_dis(pci);



	ls_pcie_drop_msg_tlp(pcie);

drivers/pci/dwc/pcie-designware.h

+25 −0
Original line number Diff line number Diff line
@@ -76,6 +76,9 @@ 
#define PCIE_ATU_FUNC(x)		(((x) & 0x7) << 16)

#define PCIE_ATU_UPPER_TARGET		0x91C



#define PCIE_MISC_CONTROL_1_OFF		0x8BC

#define PCIE_DBI_RO_WR_EN		(0x1 << 0)



/*

 * iATU Unroll-specific register definitions

 * From 4.80 core version the address translation will be made by unroll
@@ -279,6 +282,28 @@ static inline u32 dw_pcie_readl_dbi2(struct dw_pcie *pci, u32 reg) 
	return __dw_pcie_read_dbi(pci, pci->dbi_base2, reg, 0x4);

}



static inline void dw_pcie_dbi_ro_wr_en(struct dw_pcie *pci)

{

	u32 reg;

	u32 val;



	reg = PCIE_MISC_CONTROL_1_OFF;

	val = dw_pcie_readl_dbi(pci, reg);

	val |= PCIE_DBI_RO_WR_EN;

	dw_pcie_writel_dbi(pci, reg, val);

}



static inline void dw_pcie_dbi_ro_wr_dis(struct dw_pcie *pci)

{

	u32 reg;

	u32 val;



	reg = PCIE_MISC_CONTROL_1_OFF;

	val = dw_pcie_readl_dbi(pci, reg);

	val &= ~PCIE_DBI_RO_WR_EN;

	dw_pcie_writel_dbi(pci, reg, val);

}



#ifdef CONFIG_PCIE_DW_HOST

irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);

void dw_pcie_msi_init(struct pcie_port *pp);