Commit d1e86b4c authored by Giovanni Cabiddu's avatar Giovanni Cabiddu Committed by Herbert Xu
Browse files

crypto: qat - relocate GEN2 CSR access code 



Move gen2 specific transport macros to adf_gen2_hw_data.c.

Signed-off-by: default avatarGiovanni Cabiddu <giovanni.cabiddu@intel.com>
Reviewed-by: default avatarFiona Trahe <fiona.trahe@intel.com>
Reviewed-by: default avatarWojciech Ziemba <wojciech.ziemba@intel.com>
Reviewed-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent f9c697c4

drivers/crypto/qat/qat_common/adf_gen2_hw_data.c

+0 −1
Original line number Diff line number Diff line 
// SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)

/* Copyright(c) 2020 Intel Corporation */

#include "adf_gen2_hw_data.h"

#include "adf_transport_access_macros.h"



void adf_gen2_cfg_iov_thds(struct adf_accel_dev *accel_dev, bool enable,

			   int num_a_regs, int num_b_regs)

drivers/crypto/qat/qat_common/adf_gen2_hw_data.h

+68 −0
Original line number Diff line number Diff line
@@ -5,6 +5,74 @@ 


#include "adf_accel_devices.h"



/* Transport access */

#define ADF_BANK_INT_SRC_SEL_MASK_0	0x4444444CUL

#define ADF_BANK_INT_SRC_SEL_MASK_X	0x44444444UL

#define ADF_RING_CSR_RING_CONFIG	0x000

#define ADF_RING_CSR_RING_LBASE		0x040

#define ADF_RING_CSR_RING_UBASE		0x080

#define ADF_RING_CSR_RING_HEAD		0x0C0

#define ADF_RING_CSR_RING_TAIL		0x100

#define ADF_RING_CSR_E_STAT		0x14C

#define ADF_RING_CSR_INT_FLAG		0x170

#define ADF_RING_CSR_INT_SRCSEL		0x174

#define ADF_RING_CSR_INT_SRCSEL_2	0x178

#define ADF_RING_CSR_INT_COL_EN		0x17C

#define ADF_RING_CSR_INT_COL_CTL	0x180

#define ADF_RING_CSR_INT_FLAG_AND_COL	0x184

#define ADF_RING_CSR_INT_COL_CTL_ENABLE	0x80000000

#define ADF_RING_BUNDLE_SIZE		0x1000



#define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \

	ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \

		   ADF_RING_CSR_RING_HEAD + ((ring) << 2))

#define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \

	ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \

		   ADF_RING_CSR_RING_TAIL + ((ring) << 2))

#define READ_CSR_E_STAT(csr_base_addr, bank) \

	ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \

		   ADF_RING_CSR_E_STAT)

#define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \

	ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \

		   ADF_RING_CSR_RING_CONFIG + ((ring) << 2), value)

#define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \

do { \

	u32 l_base = 0, u_base = 0; \

	l_base = (u32)((value) & 0xFFFFFFFF); \

	u_base = (u32)(((value) & 0xFFFFFFFF00000000ULL) >> 32); \

	ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \

		   ADF_RING_CSR_RING_LBASE + ((ring) << 2), l_base); \

	ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \

		   ADF_RING_CSR_RING_UBASE + ((ring) << 2), u_base); \

} while (0)



#define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \

	ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \

		   ADF_RING_CSR_RING_HEAD + ((ring) << 2), value)

#define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \

	ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \

		   ADF_RING_CSR_RING_TAIL + ((ring) << 2), value)

#define WRITE_CSR_INT_FLAG(csr_base_addr, bank, value) \

	ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \

		   ADF_RING_CSR_INT_FLAG, value)

#define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \

do { \

	ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \

	ADF_RING_CSR_INT_SRCSEL, ADF_BANK_INT_SRC_SEL_MASK_0); \

	ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \

	ADF_RING_CSR_INT_SRCSEL_2, ADF_BANK_INT_SRC_SEL_MASK_X); \

} while (0)

#define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \

	ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \

		   ADF_RING_CSR_INT_COL_EN, value)

#define WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value) \

	ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \

		   ADF_RING_CSR_INT_COL_CTL, \

		   ADF_RING_CSR_INT_COL_CTL_ENABLE | (value))

#define WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value) \

	ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \

		   ADF_RING_CSR_INT_FLAG_AND_COL, value)



/* AE to function map */

#define AE2FUNCTION_MAP_A_OFFSET	(0x3A400 + 0x190)

#define AE2FUNCTION_MAP_B_OFFSET	(0x3A400 + 0x310)

drivers/crypto/qat/qat_common/adf_transport_access_macros.h

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Original line number Diff line number Diff line
@@ -4,23 +4,7 @@ 
#define ADF_TRANSPORT_ACCESS_MACROS_H



#include "adf_accel_devices.h"

#define ADF_BANK_INT_SRC_SEL_MASK_0 0x4444444CUL

#define ADF_BANK_INT_SRC_SEL_MASK_X 0x44444444UL

#define ADF_BANK_INT_FLAG_CLEAR_MASK 0xFFFF

#define ADF_RING_CSR_RING_CONFIG 0x000

#define ADF_RING_CSR_RING_LBASE 0x040

#define ADF_RING_CSR_RING_UBASE 0x080

#define ADF_RING_CSR_RING_HEAD 0x0C0

#define ADF_RING_CSR_RING_TAIL 0x100

#define ADF_RING_CSR_E_STAT 0x14C

#define ADF_RING_CSR_INT_FLAG	0x170

#define ADF_RING_CSR_INT_SRCSEL 0x174

#define ADF_RING_CSR_INT_SRCSEL_2 0x178

#define ADF_RING_CSR_INT_COL_EN 0x17C

#define ADF_RING_CSR_INT_COL_CTL 0x180

#define ADF_RING_CSR_INT_FLAG_AND_COL 0x184

#define ADF_RING_CSR_INT_COL_CTL_ENABLE	0x80000000

#define ADF_RING_BUNDLE_SIZE 0x1000

#define ADF_RING_CONFIG_NEAR_FULL_WM 0x0A

#define ADF_RING_CONFIG_NEAR_EMPTY_WM 0x05

#define ADF_COALESCING_MIN_TIME 0x1FF
@@ -74,52 +58,4 @@ 
	| size)

#define BUILD_RING_BASE_ADDR(addr, size) \

	((addr >> 6) & (0xFFFFFFFFFFFFFFFFULL << size))

#define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \

	ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \

			ADF_RING_CSR_RING_HEAD + (ring << 2))

#define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \

	ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \

			ADF_RING_CSR_RING_TAIL + (ring << 2))

#define READ_CSR_E_STAT(csr_base_addr, bank) \

	ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \

			ADF_RING_CSR_E_STAT)

#define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \

	ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \

		ADF_RING_CSR_RING_CONFIG + (ring << 2), value)

#define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \

do { \

	u32 l_base = 0, u_base = 0; \

	l_base = (u32)(value & 0xFFFFFFFF); \

	u_base = (u32)((value & 0xFFFFFFFF00000000ULL) >> 32); \

	ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \

		ADF_RING_CSR_RING_LBASE + (ring << 2), l_base);	\

	ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \

		ADF_RING_CSR_RING_UBASE + (ring << 2), u_base);	\

} while (0)

#define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \

	ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \

		ADF_RING_CSR_RING_HEAD + (ring << 2), value)

#define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \

	ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \

		ADF_RING_CSR_RING_TAIL + (ring << 2), value)

#define WRITE_CSR_INT_FLAG(csr_base_addr, bank, value) \

	ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \

			ADF_RING_CSR_INT_FLAG, value)

#define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \

do { \

	ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \

	ADF_RING_CSR_INT_SRCSEL, ADF_BANK_INT_SRC_SEL_MASK_0);	\

	ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \

	ADF_RING_CSR_INT_SRCSEL_2, ADF_BANK_INT_SRC_SEL_MASK_X); \

} while (0)

#define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \

	ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \

			ADF_RING_CSR_INT_COL_EN, value)

#define WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value) \

	ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \

			ADF_RING_CSR_INT_COL_CTL, \

			ADF_RING_CSR_INT_COL_CTL_ENABLE | value)

#define WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value) \

	ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \

			ADF_RING_CSR_INT_FLAG_AND_COL, value)

#endif