Commit f9c697c4 authored by Giovanni Cabiddu's avatar Giovanni Cabiddu Committed by Herbert Xu
Browse files

crypto: qat - split transport CSR access logic 



Abstract access to transport CSRs and move generation specific code into
adf_gen2_hw_data.c in preparation for the introduction of the qat_4xxx
driver.

Signed-off-by: default avatarGiovanni Cabiddu <giovanni.cabiddu@intel.com>
Reviewed-by: default avatarFiona Trahe <fiona.trahe@intel.com>
Reviewed-by: default avatarWojciech Ziemba <wojciech.ziemba@intel.com>
Reviewed-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent c4e84286

drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c

+1 −0
Original line number Diff line number Diff line
@@ -217,6 +217,7 @@ void adf_init_hw_data_c3xxx(struct adf_hw_device_data *hw_data) 
	hw_data->enable_vf2pf_comms = adf_pf_enable_vf2pf_comms;

	hw_data->reset_device = adf_reset_flr;

	hw_data->min_iov_compat_ver = ADF_PFVF_COMPATIBILITY_VERSION;

	adf_gen2_init_hw_csr_ops(&hw_data->csr_ops);

}



void adf_clean_hw_data_c3xxx(struct adf_hw_device_data *hw_data)

drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c

+2 −0
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ 
#include <adf_accel_devices.h>

#include <adf_pf2vf_msg.h>

#include <adf_common_drv.h>

#include <adf_gen2_hw_data.h>

#include "adf_c3xxxvf_hw_data.h"



static struct adf_hw_device_class c3xxxiov_class = {
@@ -98,6 +99,7 @@ void adf_init_hw_data_c3xxxiov(struct adf_hw_device_data *hw_data) 
	hw_data->min_iov_compat_ver = ADF_PFVF_COMPATIBILITY_VERSION;

	hw_data->dev_class->instances++;

	adf_devmgr_update_class_index(hw_data);

	adf_gen2_init_hw_csr_ops(&hw_data->csr_ops);

}



void adf_clean_hw_data_c3xxxiov(struct adf_hw_device_data *hw_data)

drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c

+1 −0
Original line number Diff line number Diff line
@@ -227,6 +227,7 @@ void adf_init_hw_data_c62x(struct adf_hw_device_data *hw_data) 
	hw_data->enable_vf2pf_comms = adf_pf_enable_vf2pf_comms;

	hw_data->reset_device = adf_reset_flr;

	hw_data->min_iov_compat_ver = ADF_PFVF_COMPATIBILITY_VERSION;

	adf_gen2_init_hw_csr_ops(&hw_data->csr_ops);

}



void adf_clean_hw_data_c62x(struct adf_hw_device_data *hw_data)

drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c

+2 −0
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ 
#include <adf_accel_devices.h>

#include <adf_pf2vf_msg.h>

#include <adf_common_drv.h>

#include <adf_gen2_hw_data.h>

#include "adf_c62xvf_hw_data.h"



static struct adf_hw_device_class c62xiov_class = {
@@ -98,6 +99,7 @@ void adf_init_hw_data_c62xiov(struct adf_hw_device_data *hw_data) 
	hw_data->min_iov_compat_ver = ADF_PFVF_COMPATIBILITY_VERSION;

	hw_data->dev_class->instances++;

	adf_devmgr_update_class_index(hw_data);

	adf_gen2_init_hw_csr_ops(&hw_data->csr_ops);

}



void adf_clean_hw_data_c62xiov(struct adf_hw_device_data *hw_data)

drivers/crypto/qat/qat_common/adf_accel_devices.h

+27 −0
Original line number Diff line number Diff line
@@ -97,6 +97,31 @@ struct adf_hw_device_class { 
	u32 instances;

} __packed;



struct adf_hw_csr_ops {

	u32 (*read_csr_ring_head)(void __iomem *csr_base_addr, u32 bank,

				  u32 ring);

	void (*write_csr_ring_head)(void __iomem *csr_base_addr, u32 bank,

				    u32 ring, u32 value);

	u32 (*read_csr_ring_tail)(void __iomem *csr_base_addr, u32 bank,

				  u32 ring);

	void (*write_csr_ring_tail)(void __iomem *csr_base_addr, u32 bank,

				    u32 ring, u32 value);

	u32 (*read_csr_e_stat)(void __iomem *csr_base_addr, u32 bank);

	void (*write_csr_ring_config)(void __iomem *csr_base_addr, u32 bank,

				      u32 ring, u32 value);

	void (*write_csr_ring_base)(void __iomem *csr_base_addr, u32 bank,

				    u32 ring, dma_addr_t addr);

	void (*write_csr_int_flag)(void __iomem *csr_base_addr, u32 bank,

				   u32 value);

	void (*write_csr_int_srcsel)(void __iomem *csr_base_addr, u32 bank);

	void (*write_csr_int_col_en)(void __iomem *csr_base_addr, u32 bank,

				     u32 value);

	void (*write_csr_int_col_ctl)(void __iomem *csr_base_addr, u32 bank,

				      u32 value);

	void (*write_csr_int_flag_and_col)(void __iomem *csr_base_addr,

					   u32 bank, u32 value);

};



struct adf_cfg_device_data;

struct adf_accel_dev;

struct adf_etr_data;
@@ -130,6 +155,7 @@ struct adf_hw_device_data { 
	void (*enable_ints)(struct adf_accel_dev *accel_dev);

	int (*enable_vf2pf_comms)(struct adf_accel_dev *accel_dev);

	void (*reset_device)(struct adf_accel_dev *accel_dev);

	struct adf_hw_csr_ops csr_ops;

	const char *fw_name;

	const char *fw_mmp_name;

	u32 fuses;
@@ -162,6 +188,7 @@ struct adf_hw_device_data { 
#define GET_NUM_RINGS_PER_BANK(accel_dev) \

	GET_HW_DATA(accel_dev)->num_rings_per_bank

#define GET_MAX_ACCELENGINES(accel_dev) (GET_HW_DATA(accel_dev)->num_engines)

#define GET_CSR_OPS(accel_dev) (&(accel_dev)->hw_device->csr_ops)

#define accel_to_pci_dev(accel_ptr) accel_ptr->accel_pci_dev.pci_dev



struct adf_admin_comms;