Unverified Commit d1debb7b authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'scmi-updates-6.7' of... 

Merge tag 'scmi-updates-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into soc/drivers

Arm SCMI updates for v6.7

Main additions this time include:

1. SCMI v3.2 clock configuration support:
   This helps to retrieve the enabled state of a clock as well as allow
   to set OEM specific clock configurations.

2. Support for generic performance scaling(DVFS):
   The current SCMI DVFS support is limited to the CPUs in the kernel.
   This extension enables it to used for all kind of devices and not
   only for the CPUs. It updates the SCMI cpufreq to utilize the power
   domain bindings. It also adds a more generic SCMI performance domain
   based on the genpd framework that as be used for all the non-CPU
   devices.

3. Extend the generic performance scaling(DVFS) support for firmware
   driver OPPs:
   Consumer drivers for devices that are attached to the SCMI performance
   domain can't make use of the current OPP library to scale performance
   as the OPPs are firmware driven and often obtained from the firmware
   rather than the device tree. These changes extend the generic OPP
   and genpd PM domain frameworks to identify and utilise these firmware
   driven OPPs.

4. SCMI v3.2 clock parent support:
   This enables the support for discovering and changing parent clocks
   and extending the SCMI clk driver to use the same.

5. Qualcom SMC/HVC transport support:
   The Qualcomm virtual platforms require capability id in the hypervisor
   call to identify which doorbell to assert when supporting multiple
   SMC/HVC based SCMI transport channels. Extra parameter is added to
   support the same and the same is obtained at the fixed address in the
   shared memory which is initialised by the firmware.

6. Move the existing SCMI power domain driver under drivers/pmdomain

Apart from the above main changes, it also include couple of minor fixes
and cosmetic reworks.

* tag 'scmi-updates-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux: (37 commits)
  firmware: arm_scmi: Add qcom smc/hvc transport support
  dt-bindings: arm: Add new compatible for smc/hvc transport for SCMI
  firmware: arm_scmi: Convert u32 to unsigned long to align with arm_smccc_1_1_invoke()
  clk: scmi: Add support for clock {set,get}_parent
  firmware: arm_scmi: Add support for clock parents
  clk: scmi: Free scmi_clk allocated when the clocks with invalid info are skipped
  firmware: arm_scpi: Use device_get_match_data()
  firmware: arm_scmi: Add generic OPP support to the SCMI performance domain
  firmware: arm_scmi: Specify the performance level when adding an OPP
  firmware: arm_scmi: Simplify error path in scmi_dvfs_device_opps_add()
  OPP: Extend support for the opp-level beyond required-opps
  OPP: Switch to use dev_pm_domain_set_performance_state()
  OPP: Extend dev_pm_opp_data with a level
  OPP: Add dev_pm_opp_add_dynamic() to allow more flexibility
  PM: domains: Implement the ->set_performance_state() callback for genpd
  PM: domains: Introduce dev_pm_domain_set_performance_state()
  firmware: arm_scmi: Rename scmi_{msg_,}clock_config_{get,set}_{2,21}
  firmware: arm_scmi: Do not use !! on boolean when setting msg->flags
  firmware: arm_scmi: Move power-domain driver to the pmdomain dir
  pmdomain: arm: Add the SCMI performance domain
  ...

Link: https://lore.kernel.org/r/20231010124347.1620040-1-sudeep.holla@arm.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 765e4aa6 da405477

Documentation/devicetree/bindings/arm/cpus.yaml

+3 −1
Original line number Diff line number Diff line
@@ -308,7 +308,9 @@ properties: 
      power-domains property.



      For PSCI based platforms, the name corresponding to the index of the PSCI

      PM domain provider, must be "psci".

      PM domain provider, must be "psci". For SCMI based platforms, the name

      corresponding to the index of an SCMI performance domain provider, must be

      "perf".



  qcom,saw:

    $ref: /schemas/types.yaml#/definitions/phandle

Documentation/devicetree/bindings/firmware/arm,scmi.yaml

+13 −2
Original line number Diff line number Diff line
@@ -38,6 +38,9 @@ properties: 
                     with shmem address(4KB-page, offset) as parameters

        items:

          - const: arm,scmi-smc-param

      - description: SCMI compliant firmware with Qualcomm SMC/HVC transport

        items:

          - const: qcom,scmi-smc

      - description: SCMI compliant firmware with SCMI Virtio transport.

                     The virtio transport only supports a single device.

        items:
@@ -149,9 +152,16 @@ properties: 
      '#clock-cells':

        const: 1



    required:

      '#power-domain-cells':

        const: 1



    oneOf:

      - required:

          - '#clock-cells'



      - required:

          - '#power-domain-cells'



  protocol@14:

    $ref: '#/$defs/protocol-node'

    unevaluatedProperties: false
@@ -306,6 +316,7 @@ else: 
          enum:

            - arm,scmi-smc

            - arm,scmi-smc-param

            - qcom,scmi-smc

  then:

    required:

      - arm,smc-id

Documentation/devicetree/bindings/power/power-domain.yaml

+9 −8
Original line number Diff line number Diff line
@@ -13,8 +13,9 @@ maintainers: 


description: |+

  System on chip designs are often divided into multiple PM domains that can be

  used for power gating of selected IP blocks for power saving by reduced leakage

  current.

  used for power gating of selected IP blocks for power saving by reduced

  leakage current. Moreover, in some cases the similar PM domains may also be

  capable of scaling performance for a group of IP blocks.



  This device tree binding can be used to bind PM domain consumer devices with

  their PM domains provided by PM domain providers. A PM domain provider can be
@@ -25,7 +26,7 @@ description: |+ 


properties:

  $nodename:

    pattern: "^(power-controller|power-domain)([@-].*)?$"

    pattern: "^(power-controller|power-domain|performance-domain)([@-].*)?$"



  domain-idle-states:

    $ref: /schemas/types.yaml#/definitions/phandle-array
@@ -44,11 +45,11 @@ properties: 


  operating-points-v2:

    description:

      Phandles to the OPP tables of power domains provided by a power domain

      provider. If the provider provides a single power domain only or all

      the power domains provided by the provider have identical OPP tables,

      then this shall contain a single phandle. Refer to ../opp/opp-v2-base.yaml

      for more information.

      Phandles to the OPP tables of power domains that are capable of scaling

      performance, provided by a power domain provider. If the provider provides

      a single power domain only or all the power domains provided by the

      provider have identical OPP tables, then this shall contain a single

      phandle. Refer to ../opp/opp-v2-base.yaml for more information.



  "#power-domain-cells":

    description:

MAINTAINERS

+1 −0
Original line number Diff line number Diff line
@@ -20904,6 +20904,7 @@ F: drivers/clk/clk-sc[mp]i.c 
F:	drivers/cpufreq/sc[mp]i-cpufreq.c

F:	drivers/firmware/arm_scmi/

F:	drivers/firmware/arm_scpi.c

F:	drivers/pmdomain/arm/

F:	drivers/powercap/arm_scmi_powercap.c

F:	drivers/regulator/scmi-regulator.c

F:	drivers/reset/reset-scmi.c

drivers/base/power/common.c

+21 −0
Original line number Diff line number Diff line
@@ -228,3 +228,24 @@ void dev_pm_domain_set(struct device *dev, struct dev_pm_domain *pd) 
	device_pm_check_callbacks(dev);

}

EXPORT_SYMBOL_GPL(dev_pm_domain_set);



/**

 * dev_pm_domain_set_performance_state - Request a new performance state.

 * @dev: The device to make the request for.

 * @state: Target performance state for the device.

 *

 * This function should be called when a new performance state needs to be

 * requested for a device that is attached to a PM domain. Note that, the

 * support for performance scaling for PM domains is optional.

 *

 * Returns 0 on success and when performance scaling isn't supported, negative

 * error code on failure.

 */

int dev_pm_domain_set_performance_state(struct device *dev, unsigned int state)

{

	if (dev->pm_domain && dev->pm_domain->set_performance_state)

		return dev->pm_domain->set_performance_state(dev, state);



	return 0;

}

EXPORT_SYMBOL_GPL(dev_pm_domain_set_performance_state);