Commit cf0a86e8 authored by Petr Machata's avatar Petr Machata Committed by David S. Miller
Browse files

mlxsw: reg: Add SGCR.lag_lookup_pgt_base 



Add SGCR.lag_lookup_pgt_base, which is used for configuring the base
address of the LAG table within the PGT table for cases when the driver
is responsible for the table placement.

Signed-off-by: default avatarPetr Machata <petrm@nvidia.com>
Reviewed-by: default avatarIdo Schimmel <idosch@nvidia.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 66eaaa85

drivers/net/ethernet/mellanox/mlxsw/reg.h

+10 −1
Original line number Diff line number Diff line
@@ -38,9 +38,18 @@ static const struct mlxsw_reg_info mlxsw_reg_##_name = { \ 


MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN);



static inline void mlxsw_reg_sgcr_pack(char *payload)

/* reg_sgcr_lag_lookup_pgt_base

 * Base address used for lookup in PGT table

 * Supported when CONFIG_PROFILE.lag_mode = 1

 * Note: when IGCR.ddd_lag_mode=0, the address shall be aligned to 8 entries.

 * Access: RW

 */

MLXSW_ITEM32(reg, sgcr, lag_lookup_pgt_base, 0x0C, 0, 16);



static inline void mlxsw_reg_sgcr_pack(char *payload, u16 lag_lookup_pgt_base)

{

	MLXSW_REG_ZERO(sgcr, payload);

	mlxsw_reg_sgcr_lag_lookup_pgt_base_set(payload, lag_lookup_pgt_base);

}



/* SPAD - Switch Physical Address Register