Commit ccf43e02 authored by Zhen Lei's avatar Zhen Lei Committed by Wei Xu
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arm64: dts: hisilicon: delete unused property smmu-cb-memtype 



The "smmu-cb-memtype" is a private property developed by the Hisilicon
driver in the early stage and is not used now. So delete it.

Otherwise, below YAML check warnings are reported:
arch/arm64/boot/dts/hisilicon/hip06-d03.dt.yaml: iommu@a0040000: \
'smmu-cb-memtype' does not match any of the regexes: 'pinctrl-[0-9]+'
arch/arm64/boot/dts/hisilicon/hip07-d05.dt.yaml: iommu@a0040000: \
'smmu-cb-memtype' does not match any of the regexes: 'pinctrl-[0-9]+'

Signed-off-by: default avatarZhen Lei <thunder.leizhen@huawei.com>
Signed-off-by: default avatarWei Xu <xuwei5@hisilicon.com>
parent b2bbc868

arch/arm64/boot/dts/hisilicon/hip06.dtsi

+0 −1
Original line number Diff line number Diff line
@@ -335,7 +335,6 @@ smmu0: iommu@a0040000 { 
		reg = <0x0 0xa0040000 0x0 0x20000>;

		#iommu-cells = <1>;

		dma-coherent;

		smmu-cb-memtype = <0x0 0x1>;

		hisilicon,broken-prefetch-cmd;

		status = "disabled";

	};

arch/arm64/boot/dts/hisilicon/hip07.dtsi

+0 −5
Original line number Diff line number Diff line
@@ -1166,7 +1166,6 @@ smmu0: iommu@a0040000 { 
		reg = <0x0 0xa0040000 0x0 0x20000>;

		#iommu-cells = <1>;

		dma-coherent;

		smmu-cb-memtype = <0x0 0x1>;

		hisilicon,broken-prefetch-cmd;

		status = "disabled";

	};
@@ -1181,7 +1180,6 @@ p0_smmu_alg_a: iommu@d0040000 { 
		#iommu-cells = <1>;

		dma-coherent;

		hisilicon,broken-prefetch-cmd;

		/* smmu-cb-memtype = <0x0 0x1>;*/

	};

	p0_smmu_alg_b: iommu@8d0040000 {

		compatible = "arm,smmu-v3";
@@ -1194,7 +1192,6 @@ p0_smmu_alg_b: iommu@8d0040000 { 
		#iommu-cells = <1>;

		dma-coherent;

		hisilicon,broken-prefetch-cmd;

		/* smmu-cb-memtype = <0x0 0x1>;*/

	};

	p1_smmu_alg_a: iommu@400d0040000 {

		compatible = "arm,smmu-v3";
@@ -1207,7 +1204,6 @@ p1_smmu_alg_a: iommu@400d0040000 { 
		#iommu-cells = <1>;

		dma-coherent;

		hisilicon,broken-prefetch-cmd;

		/* smmu-cb-memtype = <0x0 0x1>;*/

	};

	p1_smmu_alg_b: iommu@408d0040000 {

		compatible = "arm,smmu-v3";
@@ -1220,7 +1216,6 @@ p1_smmu_alg_b: iommu@408d0040000 { 
		#iommu-cells = <1>;

		dma-coherent;

		hisilicon,broken-prefetch-cmd;

		/* smmu-cb-memtype = <0x0 0x1>;*/

	};



	soc {