Commit ccc30162 authored by Dmitry Osipenko's avatar Dmitry Osipenko Committed by Thierry Reding
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media: dt: bindings: tegra-vde: Convert to schema



Convert NVIDIA Tegra video decoder binding to schema.

Reviewed-by: default avatarRob Herring <robh@kernel.org>
Acked-by: default avatarHans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: default avatarDmitry Osipenko <digetx@gmail.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 0c41e287
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NVIDIA Tegra Video Decoder Engine

Required properties:
- compatible : Must contain one of the following values:
   - "nvidia,tegra20-vde"
   - "nvidia,tegra30-vde"
   - "nvidia,tegra114-vde"
   - "nvidia,tegra124-vde"
   - "nvidia,tegra132-vde"
- reg : Must contain an entry for each entry in reg-names.
- reg-names : Must include the following entries:
  - sxe
  - bsev
  - mbe
  - ppe
  - mce
  - tfe
  - ppb
  - vdma
  - frameid
- iram : Must contain phandle to the mmio-sram device node that represents
         IRAM region used by VDE.
- interrupts : Must contain an entry for each entry in interrupt-names.
- interrupt-names : Must include the following entries:
  - sync-token
  - bsev
  - sxe
- clocks : Must include the following entries:
  - vde
- resets : Must contain an entry for each entry in reset-names.
- reset-names : Should include the following entries:
  - vde

Optional properties:
- resets : Must contain an entry for each entry in reset-names.
- reset-names : Must include the following entries:
  - mc
- iommus: Must contain phandle to the IOMMU device node.

Example:

video-codec@6001a000 {
	compatible = "nvidia,tegra20-vde";
	reg = <0x6001a000 0x1000 /* Syntax Engine */
	       0x6001b000 0x1000 /* Video Bitstream Engine */
	       0x6001c000  0x100 /* Macroblock Engine */
	       0x6001c200  0x100 /* Post-processing Engine */
	       0x6001c400  0x100 /* Motion Compensation Engine */
	       0x6001c600  0x100 /* Transform Engine */
	       0x6001c800  0x100 /* Pixel prediction block */
	       0x6001ca00  0x100 /* Video DMA */
	       0x6001d800  0x300 /* Video frame controls */>;
	reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
		    "tfe", "ppb", "vdma", "frameid";
	iram = <&vde_pool>; /* IRAM region */
	interrupts = <GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */
		     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
		     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
	interrupt-names = "sync-token", "bsev", "sxe";
	clocks = <&tegra_car TEGRA20_CLK_VDE>;
	reset-names = "vde", "mc";
	resets = <&tegra_car 61>, <&mc TEGRA20_MC_RESET_VDE>;
	iommus = <&mc TEGRA_SWGROUP_VDE>;
};
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/nvidia,tegra-vde.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra Video Decoder Engine

maintainers:
  - Dmitry Osipenko <digetx@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>
  - Thierry Reding <thierry.reding@gmail.com>

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - nvidia,tegra132-vde
              - nvidia,tegra124-vde
              - nvidia,tegra114-vde
      - items:
          - const: nvidia,tegra30-vde
          - const: nvidia,tegra20-vde
      - items:
          - const: nvidia,tegra20-vde

  reg:
    maxItems: 9

  reg-names:
    items:
      - const: sxe
      - const: bsev
      - const: mbe
      - const: ppe
      - const: mce
      - const: tfe
      - const: ppb
      - const: vdma
      - const: frameid

  clocks:
    maxItems: 1

  resets:
    maxItems: 2

  reset-names:
    items:
      - const: vde
      - const: mc

  interrupts:
    maxItems: 3

  interrupt-names:
    items:
      - const: sync-token
      - const: bsev
      - const: sxe

  iommus:
    maxItems: 1

  iram:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle of the SRAM MMIO node.

required:
  - compatible
  - reg
  - reg-names
  - clocks
  - resets
  - reset-names
  - interrupts
  - interrupt-names

additionalProperties: false

examples:
  - |
    video-codec@6001a000 {
      compatible = "nvidia,tegra20-vde";
      reg = <0x6001a000 0x1000>, /* Syntax Engine */
            <0x6001b000 0x1000>, /* Video Bitstream Engine */
            <0x6001c000  0x100>, /* Macroblock Engine */
            <0x6001c200  0x100>, /* Post-processing Engine */
            <0x6001c400  0x100>, /* Motion Compensation Engine */
            <0x6001c600  0x100>, /* Transform Engine */
            <0x6001c800  0x100>, /* Pixel prediction block */
            <0x6001ca00  0x100>, /* Video DMA */
            <0x6001d800  0x300>; /* Video frame controls */
      reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
                  "tfe", "ppb", "vdma", "frameid";
      iram = <&iram>; /* IRAM MMIO region */
      interrupts = <0  9 4>, /* Sync token */
                   <0 10 4>, /* BSE-V */
                   <0 12 4>; /* SXE */
      interrupt-names = "sync-token", "bsev", "sxe";
      clocks = <&clk 61>;
      reset-names = "vde", "mc";
      resets = <&rst 61>, <&mem 13>;
      iommus = <&mem 15>;
    };