Commit c977092a authored by Christoph Hellwig's avatar Christoph Hellwig Committed by Zhi Wang
Browse files

drm/i915/gvt: remove the map_gfn_to_mfn and set_trap_area ops 



The map_gfn_to_mfn and set_trap_area ops are never defined, so remove
them and clean up code that depends on them in the callers.

Signed-off-by: default avatarChristoph Hellwig <hch@lst.de>
Signed-off-by: default avatarZhi Wang <zhi.a.wang@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20220411141403.86980-9-hch@lst.de


Reviewed-by: default avatarJason Gunthorpe <jgg@nvidia.com>
Reviewed-by: default avatarZhi Wang <zhi.a.wang@intel.com>
parent 675e5c4a

drivers/gpu/drm/i915/gvt/cfg_space.c

+17 −72
Original line number Diff line number Diff line
@@ -129,60 +129,16 @@ int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset, 
	return 0;

}



static int map_aperture(struct intel_vgpu *vgpu, bool map)

static void map_aperture(struct intel_vgpu *vgpu, bool map)

{

	phys_addr_t aperture_pa = vgpu_aperture_pa_base(vgpu);

	unsigned long aperture_sz = vgpu_aperture_sz(vgpu);

	u64 first_gfn;

	u64 val;

	int ret;



	if (map == vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].tracked)

		return 0;



	val = vgpu_cfg_space(vgpu)[PCI_BASE_ADDRESS_2];

	if (val & PCI_BASE_ADDRESS_MEM_TYPE_64)

		val = *(u64 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_2);

	else

		val = *(u32 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_2);



	first_gfn = (val + vgpu_aperture_offset(vgpu)) >> PAGE_SHIFT;



	ret = intel_gvt_hypervisor_map_gfn_to_mfn(vgpu, first_gfn,

						  aperture_pa >> PAGE_SHIFT,

						  aperture_sz >> PAGE_SHIFT,

						  map);

	if (ret)

		return ret;



	if (map != vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].tracked)

		vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].tracked = map;

	return 0;

}



static int trap_gttmmio(struct intel_vgpu *vgpu, bool trap)

static void trap_gttmmio(struct intel_vgpu *vgpu, bool trap)

{

	u64 start, end;

	u64 val;

	int ret;



	if (trap == vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].tracked)

		return 0;



	val = vgpu_cfg_space(vgpu)[PCI_BASE_ADDRESS_0];

	if (val & PCI_BASE_ADDRESS_MEM_TYPE_64)

		start = *(u64 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_0);

	else

		start = *(u32 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_0);



	start &= ~GENMASK(3, 0);

	end = start + vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].size - 1;



	ret = intel_gvt_hypervisor_set_trap_area(vgpu, start, end, trap);

	if (ret)

		return ret;



	if (trap != vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].tracked)

		vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].tracked = trap;

	return 0;

}



static int emulate_pci_command_write(struct intel_vgpu *vgpu,
@@ -191,26 +147,17 @@ static int emulate_pci_command_write(struct intel_vgpu *vgpu, 
	u8 old = vgpu_cfg_space(vgpu)[offset];

	u8 new = *(u8 *)p_data;

	u8 changed = old ^ new;

	int ret;



	vgpu_pci_cfg_mem_write(vgpu, offset, p_data, bytes);

	if (!(changed & PCI_COMMAND_MEMORY))

		return 0;



	if (old & PCI_COMMAND_MEMORY) {

		ret = trap_gttmmio(vgpu, false);

		if (ret)

			return ret;

		ret = map_aperture(vgpu, false);

		if (ret)

			return ret;

		trap_gttmmio(vgpu, false);

		map_aperture(vgpu, false);

	} else {

		ret = trap_gttmmio(vgpu, true);

		if (ret)

			return ret;

		ret = map_aperture(vgpu, true);

		if (ret)

			return ret;

		trap_gttmmio(vgpu, true);

		map_aperture(vgpu, true);

	}



	return 0;
@@ -230,13 +177,12 @@ static int emulate_pci_rom_bar_write(struct intel_vgpu *vgpu, 
	return 0;

}



static int emulate_pci_bar_write(struct intel_vgpu *vgpu, unsigned int offset,

static void emulate_pci_bar_write(struct intel_vgpu *vgpu, unsigned int offset,

	void *p_data, unsigned int bytes)

{

	u32 new = *(u32 *)(p_data);

	bool lo = IS_ALIGNED(offset, 8);

	u64 size;

	int ret = 0;

	bool mmio_enabled =

		vgpu_cfg_space(vgpu)[PCI_COMMAND] & PCI_COMMAND_MEMORY;

	struct intel_vgpu_pci_bar *bars = vgpu->cfg_space.bar;
@@ -259,14 +205,14 @@ static int emulate_pci_bar_write(struct intel_vgpu *vgpu, unsigned int offset, 
			 * Untrap the BAR, since guest hasn't configured a

			 * valid GPA

			 */

			ret = trap_gttmmio(vgpu, false);

			trap_gttmmio(vgpu, false);

			break;

		case PCI_BASE_ADDRESS_2:

		case PCI_BASE_ADDRESS_3:

			size = ~(bars[INTEL_GVT_PCI_BAR_APERTURE].size -1);

			intel_vgpu_write_pci_bar(vgpu, offset,

						size >> (lo ? 0 : 32), lo);

			ret = map_aperture(vgpu, false);

			map_aperture(vgpu, false);

			break;

		default:

			/* Unimplemented BARs */
@@ -282,19 +228,18 @@ static int emulate_pci_bar_write(struct intel_vgpu *vgpu, unsigned int offset, 
			 */

			trap_gttmmio(vgpu, false);

			intel_vgpu_write_pci_bar(vgpu, offset, new, lo);

			ret = trap_gttmmio(vgpu, mmio_enabled);

			trap_gttmmio(vgpu, mmio_enabled);

			break;

		case PCI_BASE_ADDRESS_2:

		case PCI_BASE_ADDRESS_3:

			map_aperture(vgpu, false);

			intel_vgpu_write_pci_bar(vgpu, offset, new, lo);

			ret = map_aperture(vgpu, mmio_enabled);

			map_aperture(vgpu, mmio_enabled);

			break;

		default:

			intel_vgpu_write_pci_bar(vgpu, offset, new, lo);

		}

	}

	return ret;

}



/**
@@ -336,8 +281,8 @@ int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset, 
	case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_5:

		if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4)))

			return -EINVAL;

		return emulate_pci_bar_write(vgpu, offset, p_data, bytes);



		emulate_pci_bar_write(vgpu, offset, p_data, bytes);

		break;

	case INTEL_GVT_PCI_SWSCI:

		if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4)))

			return -EINVAL;

drivers/gpu/drm/i915/gvt/hypercall.h

+0 −4
Original line number Diff line number Diff line
@@ -62,10 +62,6 @@ struct intel_gvt_mpt { 


	int (*dma_pin_guest_page)(unsigned long handle, dma_addr_t dma_addr);



	int (*map_gfn_to_mfn)(unsigned long handle, unsigned long gfn,

			      unsigned long mfn, unsigned int nr, bool map);

	int (*set_trap_area)(unsigned long handle, u64 start, u64 end,

			     bool map);

	int (*set_opregion)(void *vgpu);

	int (*set_edid)(void *vgpu, int port_num);

	int (*get_vfio_device)(void *vgpu);

drivers/gpu/drm/i915/gvt/mpt.h

+0 −44
Original line number Diff line number Diff line
@@ -270,50 +270,6 @@ intel_gvt_hypervisor_dma_pin_guest_page(struct intel_vgpu *vgpu, 
	return intel_gvt_host.mpt->dma_pin_guest_page(vgpu->handle, dma_addr);

}



/**

 * intel_gvt_hypervisor_map_gfn_to_mfn - map a GFN region to MFN

 * @vgpu: a vGPU

 * @gfn: guest PFN

 * @mfn: host PFN

 * @nr: amount of PFNs

 * @map: map or unmap

 *

 * Returns:

 * Zero on success, negative error code if failed.

 */

static inline int intel_gvt_hypervisor_map_gfn_to_mfn(

		struct intel_vgpu *vgpu, unsigned long gfn,

		unsigned long mfn, unsigned int nr,

		bool map)

{

	/* a MPT implementation could have MMIO mapped elsewhere */

	if (!intel_gvt_host.mpt->map_gfn_to_mfn)

		return 0;



	return intel_gvt_host.mpt->map_gfn_to_mfn(vgpu->handle, gfn, mfn, nr,

						  map);

}



/**

 * intel_gvt_hypervisor_set_trap_area - Trap a guest PA region

 * @vgpu: a vGPU

 * @start: the beginning of the guest physical address region

 * @end: the end of the guest physical address region

 * @map: map or unmap

 *

 * Returns:

 * Zero on success, negative error code if failed.

 */

static inline int intel_gvt_hypervisor_set_trap_area(

		struct intel_vgpu *vgpu, u64 start, u64 end, bool map)

{

	/* a MPT implementation could have MMIO trapped elsewhere */

	if (!intel_gvt_host.mpt->set_trap_area)

		return 0;



	return intel_gvt_host.mpt->set_trap_area(vgpu->handle, start, end, map);

}



/**

 * intel_gvt_hypervisor_set_opregion - Set opregion for guest

 * @vgpu: a vGPU