Commit c910a717 authored by Dmytro Laktyushkin's avatar Dmytro Laktyushkin Committed by Alex Deucher
Browse files

drm/amd/display: clean up set_bandwidth usage 



This removes redundant set_bandwidth calls as well
as fixes a bug in post_set_address_update where dcn1
would never get to lower clocks.

Signed-off-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: default avatarNikola Cornij <Nikola.Cornij@amd.com>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 3cdecd45

drivers/gpu/drm/amd/display/dc/core/dc.c

+0 −5
Original line number Diff line number Diff line
@@ -944,12 +944,7 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc) 


	dc->optimized_required = false;



	/* 3rd param should be true, temp w/a for RV*/

#if defined(CONFIG_DRM_AMD_DC_DCN1_0)

	dc->hwss.set_bandwidth(dc, context, dc->ctx->dce_version < DCN_VERSION_1_0);

#else

	dc->hwss.set_bandwidth(dc, context, true);

#endif

	return true;

}

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

+0 −5
Original line number Diff line number Diff line
@@ -2036,8 +2036,6 @@ enum dc_status dce110_apply_ctx_to_hw( 
	if (dc->fbc_compressor)

		dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);



	dc->hwss.set_bandwidth(dc, context, false);



	dce110_setup_audio_dto(dc, context);



	for (i = 0; i < dc->res_pool->pipe_count; i++) {
@@ -2066,9 +2064,6 @@ enum dc_status dce110_apply_ctx_to_hw( 
			return status;

	}



	/* to save power */

	dc->hwss.set_bandwidth(dc, context, true);



	dcb->funcs->set_scratch_critical_state(dcb, false);



	if (dc->fbc_compressor)

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

+3 −8
Original line number Diff line number Diff line
@@ -2268,8 +2268,7 @@ static void dcn10_apply_ctx_for_surface( 
			hwss1_plane_atomic_disconnect(dc, old_pipe_ctx);

			removed_pipe[i] = true;



			DC_LOG_DC(

					"Reset mpcc for pipe %d\n",

			DC_LOG_DC("Reset mpcc for pipe %d\n",

					old_pipe_ctx->pipe_idx);

		}

	}
@@ -2365,9 +2364,8 @@ static void dcn10_set_bandwidth( 
		struct dc_state *context,

		bool decrease_allowed)

{

	if (dc->debug.sanity_checks) {

	if (dc->debug.sanity_checks)

		dcn10_verify_allow_pstate_change_high(dc);

	}



	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))

		return;
@@ -2382,13 +2380,10 @@ static void dcn10_set_bandwidth( 


	dcn10_pplib_apply_display_requirements(dc, context);



	if (dc->debug.sanity_checks) {

	if (dc->debug.sanity_checks)

		dcn10_verify_allow_pstate_change_high(dc);

}



	/* need to fix this function.  not doing the right thing here */

}



static void set_drr(struct pipe_ctx **pipe_ctx,

		int num_pipes, int vmin, int vmax)

{