Commit 3cdecd45 authored by Dmytro Laktyushkin's avatar Dmytro Laktyushkin Committed by Alex Deucher
Browse files

drm/amd/display: rename dce_disp_clk to dccg 



No functional change.

Signed-off-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: default avatarNikola Cornij <Nikola.Cornij@amd.com>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 472800a0

drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c

+51 −64
Original line number Diff line number Diff line
@@ -139,29 +139,6 @@ static int dentist_get_divider_from_did(int did) 
	}

}



static int dce_clocks_get_dp_ref_freq(struct dccg *clk)

{

	struct dce_dccg *clk_dce = TO_DCE_CLOCKS(clk);

	int dprefclk_wdivider;

	int dprefclk_src_sel;

	int dp_ref_clk_khz = 600000;

	int target_div;



	/* ASSERT DP Reference Clock source is from DFS*/

	REG_GET(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, &dprefclk_src_sel);

	ASSERT(dprefclk_src_sel == 0);



	/* Read the mmDENTIST_DISPCLK_CNTL to get the currently

	 * programmed DID DENTIST_DPREFCLK_WDIVIDER*/

	REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, &dprefclk_wdivider);



	/* Convert DENTIST_DPREFCLK_WDIVIDERto actual divider*/

	target_div = dentist_get_divider_from_did(dprefclk_wdivider);



	/* Calculate the current DFS clock, in kHz.*/

	dp_ref_clk_khz = (dentist_divider_range_scale_factor

		* clk_dce->dentist_vco_freq_khz) / target_div;



/* SW will adjust DP REF Clock average value for all purposes

 * (DP DTO / DP Audio DTO and DP GTC)

 if clock is spread for all cases:
@@ -174,6 +151,8 @@ static int dce_clocks_get_dp_ref_freq(struct dccg *clk) 
 (should not be case with CIK) then SW should program all rates

 generated according to average value (case as with previous ASICs)

  */

static int dccg_adjust_dp_ref_freq_for_ss(struct dce_dccg *clk_dce, int dp_ref_clk_khz)

{

	if (clk_dce->ss_on_dprefclk && clk_dce->dprefclk_ss_divider != 0) {

		struct fixed31_32 ss_percentage = dc_fixpt_div_int(

				dc_fixpt_from_fraction(clk_dce->dprefclk_ss_percentage,
@@ -184,32 +163,42 @@ static int dce_clocks_get_dp_ref_freq(struct dccg *clk) 
		adj_dp_ref_clk_khz = dc_fixpt_mul_int(ss_percentage, dp_ref_clk_khz);

		dp_ref_clk_khz = dc_fixpt_floor(adj_dp_ref_clk_khz);

	}



	return dp_ref_clk_khz;

}



/* TODO: This is DCN DPREFCLK: it could be program by DENTIST by VBIOS

 * or CLK0_CLK11 by SMU. For DCE120, it is wlays 600Mhz. Will re-visit

 * clock implementation

 */

static int dce_clocks_get_dp_ref_freq_wrkaround(struct dccg *clk)

static int dce_get_dp_ref_freq_khz(struct dccg *clk)

{

	struct dce_dccg *clk_dce = TO_DCE_CLOCKS(clk);

	int dprefclk_wdivider;

	int dprefclk_src_sel;

	int dp_ref_clk_khz = 600000;

	int target_div;



	if (clk_dce->ss_on_dprefclk && clk_dce->dprefclk_ss_divider != 0) {

		struct fixed31_32 ss_percentage = dc_fixpt_div_int(

				dc_fixpt_from_fraction(clk_dce->dprefclk_ss_percentage,

						clk_dce->dprefclk_ss_divider), 200);

		struct fixed31_32 adj_dp_ref_clk_khz;

	/* ASSERT DP Reference Clock source is from DFS*/

	REG_GET(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, &dprefclk_src_sel);

	ASSERT(dprefclk_src_sel == 0);



		ss_percentage = dc_fixpt_sub(dc_fixpt_one, ss_percentage);

		adj_dp_ref_clk_khz = dc_fixpt_mul_int(ss_percentage, dp_ref_clk_khz);

		dp_ref_clk_khz = dc_fixpt_floor(adj_dp_ref_clk_khz);

	/* Read the mmDENTIST_DISPCLK_CNTL to get the currently

	 * programmed DID DENTIST_DPREFCLK_WDIVIDER*/

	REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, &dprefclk_wdivider);



	/* Convert DENTIST_DPREFCLK_WDIVIDERto actual divider*/

	target_div = dentist_get_divider_from_did(dprefclk_wdivider);



	/* Calculate the current DFS clock, in kHz.*/

	dp_ref_clk_khz = (dentist_divider_range_scale_factor

		* clk_dce->dentist_vco_freq_khz) / target_div;



	return dccg_adjust_dp_ref_freq_for_ss(clk_dce, dp_ref_clk_khz);

}



	return dp_ref_clk_khz;

static int dce12_get_dp_ref_freq_khz(struct dccg *clk)

{

	struct dce_dccg *clk_dce = TO_DCE_CLOCKS(clk);



	return dccg_adjust_dp_ref_freq_for_ss(clk_dce, 600000);

}



static enum dm_pp_clocks_state dce_get_required_clocks_state(

	struct dccg *clk,

	struct dc_clocks *req_clocks)
@@ -590,8 +579,7 @@ static void dcn1_update_clocks(struct dccg *dccg, 
	/* make sure dcf clk is before dpp clk to

	 * make sure we have enough voltage to run dpp clk

	 */

	if (send_request_to_increase

		) {

	if (send_request_to_increase) {

		/*use dcfclk to request voltage*/

		clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DCFCLK;

		clock_voltage_req.clocks_in_khz = dcn_find_dcfclk_suits_all(dc, new_clocks);
@@ -644,8 +632,7 @@ static void dcn1_update_clocks(struct dccg *dccg, 
	}



#ifdef CONFIG_DRM_AMD_DC_DCN1_0

	if (!send_request_to_increase && send_request_to_lower

		) {

	if (!send_request_to_increase && send_request_to_lower) {

		/*use dcfclk to request voltage*/

		clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DCFCLK;

		clock_voltage_req.clocks_in_khz = dcn_find_dcfclk_suits_all(dc, new_clocks);
@@ -685,31 +672,31 @@ static void dce_update_clocks(struct dccg *dccg, 
}



static const struct display_clock_funcs dcn1_funcs = {

	.get_dp_ref_clk_frequency = dce_clocks_get_dp_ref_freq_wrkaround,

	.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,

	.set_dispclk = dce112_set_clock,

	.update_clocks = dcn1_update_clocks

};



static const struct display_clock_funcs dce120_funcs = {

	.get_dp_ref_clk_frequency = dce_clocks_get_dp_ref_freq_wrkaround,

	.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,

	.set_dispclk = dce112_set_clock,

	.update_clocks = dce12_update_clocks

};



static const struct display_clock_funcs dce112_funcs = {

	.get_dp_ref_clk_frequency = dce_clocks_get_dp_ref_freq,

	.get_dp_ref_clk_frequency = dce_get_dp_ref_freq_khz,

	.set_dispclk = dce112_set_clock,

	.update_clocks = dce_update_clocks

};



static const struct display_clock_funcs dce110_funcs = {

	.get_dp_ref_clk_frequency = dce_clocks_get_dp_ref_freq,

	.get_dp_ref_clk_frequency = dce_get_dp_ref_freq_khz,

	.set_dispclk = dce_psr_set_clock,

	.update_clocks = dce_update_clocks

};



static const struct display_clock_funcs dce_funcs = {

	.get_dp_ref_clk_frequency = dce_clocks_get_dp_ref_freq,

	.get_dp_ref_clk_frequency = dce_get_dp_ref_freq_khz,

	.set_dispclk = dce_set_clock,

	.update_clocks = dce_update_clocks

};
@@ -717,9 +704,9 @@ static const struct display_clock_funcs dce_funcs = { 
static void dce_dccg_construct(

	struct dce_dccg *clk_dce,

	struct dc_context *ctx,

	const struct dce_disp_clk_registers *regs,

	const struct dce_disp_clk_shift *clk_shift,

	const struct dce_disp_clk_mask *clk_mask)

	const struct dccg_registers *regs,

	const struct dccg_shift *clk_shift,

	const struct dccg_mask *clk_mask)

{

	struct dccg *base = &clk_dce->base;
@@ -745,9 +732,9 @@ static void dce_dccg_construct( 


struct dccg *dce_dccg_create(

	struct dc_context *ctx,

	const struct dce_disp_clk_registers *regs,

	const struct dce_disp_clk_shift *clk_shift,

	const struct dce_disp_clk_mask *clk_mask)

	const struct dccg_registers *regs,

	const struct dccg_shift *clk_shift,

	const struct dccg_mask *clk_mask)

{

	struct dce_dccg *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);
@@ -768,9 +755,9 @@ struct dccg *dce_dccg_create( 


struct dccg *dce110_dccg_create(

	struct dc_context *ctx,

	const struct dce_disp_clk_registers *regs,

	const struct dce_disp_clk_shift *clk_shift,

	const struct dce_disp_clk_mask *clk_mask)

	const struct dccg_registers *regs,

	const struct dccg_shift *clk_shift,

	const struct dccg_mask *clk_mask)

{

	struct dce_dccg *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);
@@ -793,9 +780,9 @@ struct dccg *dce110_dccg_create( 


struct dccg *dce112_dccg_create(

	struct dc_context *ctx,

	const struct dce_disp_clk_registers *regs,

	const struct dce_disp_clk_shift *clk_shift,

	const struct dce_disp_clk_mask *clk_mask)

	const struct dccg_registers *regs,

	const struct dccg_shift *clk_shift,

	const struct dccg_mask *clk_mask)

{

	struct dce_dccg *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);

drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h

+25 −16
Original line number Diff line number Diff line
@@ -33,6 +33,9 @@ 
	.DPREFCLK_CNTL = mmDPREFCLK_CNTL, \

	.DENTIST_DISPCLK_CNTL = mmDENTIST_DISPCLK_CNTL



#define CLK_COMMON_REG_LIST_DCN_BASE() \

	SR(DENTIST_DISPCLK_CNTL)



#define CLK_SF(reg_name, field_name, post_fix)\

	.field_name = reg_name ## __ ## field_name ## post_fix
@@ -40,28 +43,34 @@ 
	CLK_SF(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, mask_sh), \

	CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, mask_sh)



#define CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh) \

	CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, mask_sh),\

	CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, mask_sh)



#define CLK_REG_FIELD_LIST(type) \

	type DPREFCLK_SRC_SEL; \

	type DENTIST_DPREFCLK_WDIVIDER;

	type DENTIST_DPREFCLK_WDIVIDER; \

	type DENTIST_DISPCLK_WDIVIDER; \

	type DENTIST_DPPCLK_WDIVIDER;



struct dce_disp_clk_shift {

struct dccg_shift {

	CLK_REG_FIELD_LIST(uint8_t)

};



struct dce_disp_clk_mask {

struct dccg_mask {

	CLK_REG_FIELD_LIST(uint32_t)

};



struct dce_disp_clk_registers {

struct dccg_registers {

	uint32_t DPREFCLK_CNTL;

	uint32_t DENTIST_DISPCLK_CNTL;

};



struct dce_dccg {

	struct dccg base;

	const struct dce_disp_clk_registers *regs;

	const struct dce_disp_clk_shift *clk_shift;

	const struct dce_disp_clk_mask *clk_mask;

	const struct dccg_registers *regs;

	const struct dccg_shift *clk_shift;

	const struct dccg_mask *clk_mask;



	struct state_dependent_clocks max_clks_by_state[DM_PP_CLOCKS_MAX_STATES];
@@ -84,21 +93,21 @@ struct dce_dccg { 


struct dccg *dce_dccg_create(

	struct dc_context *ctx,

	const struct dce_disp_clk_registers *regs,

	const struct dce_disp_clk_shift *clk_shift,

	const struct dce_disp_clk_mask *clk_mask);

	const struct dccg_registers *regs,

	const struct dccg_shift *clk_shift,

	const struct dccg_mask *clk_mask);



struct dccg *dce110_dccg_create(

	struct dc_context *ctx,

	const struct dce_disp_clk_registers *regs,

	const struct dce_disp_clk_shift *clk_shift,

	const struct dce_disp_clk_mask *clk_mask);

	const struct dccg_registers *regs,

	const struct dccg_shift *clk_shift,

	const struct dccg_mask *clk_mask);



struct dccg *dce112_dccg_create(

	struct dc_context *ctx,

	const struct dce_disp_clk_registers *regs,

	const struct dce_disp_clk_shift *clk_shift,

	const struct dce_disp_clk_mask *clk_mask);

	const struct dccg_registers *regs,

	const struct dccg_shift *clk_shift,

	const struct dccg_mask *clk_mask);



struct dccg *dce120_dccg_create(struct dc_context *ctx);

drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h

+0 −3
Original line number Diff line number Diff line
@@ -249,7 +249,6 @@ struct dce_hwseq_registers { 
	uint32_t DISPCLK_FREQ_CHANGE_CNTL;

	uint32_t RBBMIF_TIMEOUT_DIS;

	uint32_t RBBMIF_TIMEOUT_DIS_2;

	uint32_t DENTIST_DISPCLK_CNTL;

	uint32_t DCHUBBUB_CRC_CTRL;

	uint32_t DPP_TOP0_DPP_CRC_CTRL;

	uint32_t DPP_TOP0_DPP_CRC_VAL_R_G;
@@ -496,8 +495,6 @@ struct dce_hwseq_registers { 
	type DOMAIN7_PGFSM_PWR_STATUS; \

	type DCFCLK_GATE_DIS; \

	type DCHUBBUB_GLOBAL_TIMER_REFDIV; \

	type DENTIST_DPPCLK_WDIVIDER; \

	type DENTIST_DISPCLK_WDIVIDER; \

	type VGA_TEST_ENABLE; \

	type VGA_TEST_RENDER_START; \

	type D1VGA_MODE_ENABLE; \

drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c

+3 −3
Original line number Diff line number Diff line
@@ -135,15 +135,15 @@ static const struct dce110_timing_generator_offsets dce100_tg_offsets[] = { 
	.reg_name = mm ## block ## id ## _ ## reg_name





static const struct dce_disp_clk_registers disp_clk_regs = {

static const struct dccg_registers disp_clk_regs = {

		CLK_COMMON_REG_LIST_DCE_BASE()

};



static const struct dce_disp_clk_shift disp_clk_shift = {

static const struct dccg_shift disp_clk_shift = {

		CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)

};



static const struct dce_disp_clk_mask disp_clk_mask = {

static const struct dccg_mask disp_clk_mask = {

		CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)

};

drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c

+3 −3
Original line number Diff line number Diff line
@@ -146,15 +146,15 @@ static const struct dce110_timing_generator_offsets dce110_tg_offsets[] = { 
#define SRI(reg_name, block, id)\

	.reg_name = mm ## block ## id ## _ ## reg_name



static const struct dce_disp_clk_registers disp_clk_regs = {

static const struct dccg_registers disp_clk_regs = {

		CLK_COMMON_REG_LIST_DCE_BASE()

};



static const struct dce_disp_clk_shift disp_clk_shift = {

static const struct dccg_shift disp_clk_shift = {

		CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)

};



static const struct dce_disp_clk_mask disp_clk_mask = {

static const struct dccg_mask disp_clk_mask = {

		CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)

};