Commit c4cbd035 authored by Zhen Lei's avatar Zhen Lei Committed by Wei Xu
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arm64: dts: hisilicon: list all clocks required by snps-dw-apb-uart.yaml 



The snps,dw-apb-uart binding need to specify two clocks: "baudclk",
"apb_pclk". But only "apb_pclk" is specified now. Because the driver
preferentially matches the first clock. Otherwise, it matches the second
clock instead of both clocks. So both of them use the same clock don't
change the function.

Signed-off-by: default avatarZhen Lei <thunder.leizhen@huawei.com>
Signed-off-by: default avatarWei Xu <xuwei5@hisilicon.com>
parent 58dd4736

arch/arm64/boot/dts/hisilicon/hip05.dtsi

+4 −4
Original line number Diff line number Diff line
@@ -300,8 +300,8 @@ uart0: serial@80300000 { 
			compatible = "snps,dw-apb-uart";

			reg = <0x0 0x80300000 0x0 0x10000>;

			interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&refclk200mhz>;

			clock-names = "apb_pclk";

			clocks = <&refclk200mhz>, <&refclk200mhz>;

			clock-names = "baudclk", "apb_pclk";

			reg-shift = <2>;

			reg-io-width = <4>;

			status = "disabled";
@@ -311,8 +311,8 @@ uart1: serial@80310000 { 
			compatible = "snps,dw-apb-uart";

			reg = <0x0 0x80310000 0x0 0x10000>;

			interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&refclk200mhz>;

			clock-names = "apb_pclk";

			clocks = <&refclk200mhz>, <&refclk200mhz>;

			clock-names = "baudclk", "apb_pclk";

			reg-shift = <2>;

			reg-io-width = <4>;

			status = "disabled";