Commit c3852566 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven
Browse files

pinctrl: renesas: rzg2l: Rename rzg2l_gpio_configs[] 



The rzg2l_gpio_configs array is really related to the RZ/G2L (R9A07G044)
Soc only.  Hence rename it to r9a07g044_gpio_configs[].

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/19958e63a2b793be5182640c4301ec5a77a507f6.1695369116.git.geert+renesas@glider.be
parent dd462cf5

drivers/pinctrl/renesas/pinctrl-rzg2l.c

+5 −5
Original line number Diff line number Diff line
@@ -985,7 +985,7 @@ static const char * const rzg2l_gpio_names[] = { 
	"P48_0", "P48_1", "P48_2", "P48_3", "P48_4", "P48_5", "P48_6", "P48_7",

};



static const u32 rzg2l_gpio_configs[] = {

static const u32 r9a07g044_gpio_configs[] = {

	RZG2L_GPIO_PORT_PACK(2, 0x10, RZG2L_MPXED_PIN_FUNCS),

	RZG2L_GPIO_PORT_PACK(2, 0x11, RZG2L_MPXED_PIN_FUNCS),

	RZG2L_GPIO_PORT_PACK(2, 0x12, RZG2L_MPXED_PIN_FUNCS),
@@ -1485,7 +1485,7 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev) 
	struct clk *clk;

	int ret;



	BUILD_BUG_ON(ARRAY_SIZE(rzg2l_gpio_configs) * RZG2L_PINS_PER_PORT >

	BUILD_BUG_ON(ARRAY_SIZE(r9a07g044_gpio_configs) * RZG2L_PINS_PER_PORT >

		     ARRAY_SIZE(rzg2l_gpio_names));



	BUILD_BUG_ON(ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT >
@@ -1535,10 +1535,10 @@ static struct rzg2l_pinctrl_data r9a07g043_data = { 


static struct rzg2l_pinctrl_data r9a07g044_data = {

	.port_pins = rzg2l_gpio_names,

	.port_pin_configs = rzg2l_gpio_configs,

	.n_ports = ARRAY_SIZE(rzg2l_gpio_configs),

	.port_pin_configs = r9a07g044_gpio_configs,

	.n_ports = ARRAY_SIZE(r9a07g044_gpio_configs),

	.dedicated_pins = rzg2l_dedicated_pins.common,

	.n_port_pins = ARRAY_SIZE(rzg2l_gpio_configs) * RZG2L_PINS_PER_PORT,

	.n_port_pins = ARRAY_SIZE(r9a07g044_gpio_configs) * RZG2L_PINS_PER_PORT,

	.n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) +

		ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins),

};