Commit dd462cf5 authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
Browse files

pinctrl: renesas: rzg2l: Make reverse order of enable() for disable() 



We usually do reverse order of enable() for disable(). Currently, the
ordering of irq_chip_disable_parent() is not correct in
rzg2l_gpio_irq_disable(). Fix the incorrect order.

Fixes: db2e5f21 ("pinctrl: renesas: pinctrl-rzg2l: Add IRQ domain to handle GPIO interrupt")
Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Tested-by: default avatarClaudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230918123355.262115-2-biju.das.jz@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 84c580e9

drivers/pinctrl/renesas/pinctrl-rzg2l.c

+2 −1
Original line number Diff line number Diff line
@@ -1175,6 +1175,8 @@ static void rzg2l_gpio_irq_disable(struct irq_data *d) 
	u32 port;

	u8 bit;



	irq_chip_disable_parent(d);



	port = RZG2L_PIN_ID_TO_PORT(hwirq);

	bit = RZG2L_PIN_ID_TO_PIN(hwirq);
@@ -1189,7 +1191,6 @@ static void rzg2l_gpio_irq_disable(struct irq_data *d) 
	spin_unlock_irqrestore(&pctrl->lock, flags);



	gpiochip_disable_irq(gc, hwirq);

	irq_chip_disable_parent(d);

}



static void rzg2l_gpio_irq_enable(struct irq_data *d)