Commit c0af8c74 authored by Ovidiu Bunea's avatar Ovidiu Bunea Committed by Alex Deucher
Browse files

drm/amd/display: Make driver backwards-compatible with non-IPS PMFW 



[why]
Driver needs to be compatible with PM FW that doesn't support IPS

[how]
Toggle internal control flag

Reviewed-by: default avatarCharlene Liu <charlene.liu@amd.com>
Acked-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: default avatarOvidiu Bunea <ovidiu.bunea@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 6ec87647

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

+18 −10
Original line number Diff line number Diff line
@@ -744,16 +744,16 @@ static void dcn35_set_idle_state(struct clk_mgr *clk_mgr_base, bool allow_idle) 
	struct dc *dc = clk_mgr_base->ctx->dc;

	uint32_t val = dcn35_smu_read_ips_scratch(clk_mgr);



	if (dc->debug.disable_ips == 0) {

	if (dc->config.disable_ips == 0) {

		val |= DMUB_IPS1_ALLOW_MASK;

		val |= DMUB_IPS2_ALLOW_MASK;

	} else if (dc->debug.disable_ips == DMUB_IPS_DISABLE_IPS1) {

	} else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS1) {

		val = val & ~DMUB_IPS1_ALLOW_MASK;

		val = val & ~DMUB_IPS2_ALLOW_MASK;

	} else if (dc->debug.disable_ips == DMUB_IPS_DISABLE_IPS2) {

	} else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS2) {

		val |= DMUB_IPS1_ALLOW_MASK;

		val = val & ~DMUB_IPS2_ALLOW_MASK;

	} else if (dc->debug.disable_ips == DMUB_IPS_DISABLE_IPS2_Z10) {

	} else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS2_Z10) {

		val |= DMUB_IPS1_ALLOW_MASK;

		val |= DMUB_IPS2_ALLOW_MASK;

	}
@@ -1036,12 +1036,20 @@ void dcn35_clk_mgr_construct( 
		dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,

				smu_dpm_clks.dpm_clks);



	if (dcn35_smu_get_ips_supported(&clk_mgr->base)) {

	if (ctx->dc->config.disable_ips == 0) {

		bool ips_support = false;



		/*avoid call pmfw at init*/

		ips_support = dcn35_smu_get_ips_supported(&clk_mgr->base);

		if (ips_support) {

			ctx->dc->debug.ignore_pg = false;

		ctx->dc->debug.dmcub_emulation = false;

			ctx->dc->debug.disable_dpp_power_gate = false;

			ctx->dc->debug.disable_hubp_power_gate = false;

			ctx->dc->debug.disable_dsc_power_gate = false;

		} else {

			/*let's reset the config control flag*/

			ctx->dc->config.disable_ips = 1; /*pmfw not support it, disable it all*/

		}

	}

}

drivers/gpu/drm/amd/display/dc/dc.h

+1 −1
Original line number Diff line number Diff line
@@ -423,6 +423,7 @@ struct dc_config { 
	bool dc_mode_clk_limit_support;

	bool EnableMinDispClkODM;

	bool enable_auto_dpm_test_logs;

	unsigned int disable_ips;

};



enum visual_confirm {
@@ -913,7 +914,6 @@ struct dc_debug_options { 
	enum det_size crb_alloc_policy;

	int crb_alloc_policy_min_disp_count;

	bool disable_z10;

	unsigned int disable_ips;

	bool enable_z9_disable_interface;

	bool psr_skip_crtc_disable;

	union dpia_debug_options dpia_debug;

drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c

+0 −1
Original line number Diff line number Diff line
@@ -747,7 +747,6 @@ static const struct dc_debug_options debug_defaults_drv = { 
	.disable_z10 = false,

	.ignore_pg = true,

	.psp_disabled_wa = true,

	.disable_ips = true,

	.ips2_eval_delay_us = 200,

	.ips2_entry_delay_us = 400

};