Commit bff4e5da authored by Wolfram Sang's avatar Wolfram Sang Committed by Geert Uytterhoeven
Browse files

arm64: dts: renesas: r8a779a0: Add & update SCIF nodes 



This is the result of multiple patches taken from the BSP, combined,
rebased, and properly sorted. SCIF0 gets DMA properties, other SCIFs are
entirely new.

Signed-off-by: default avatarLinh Phung <linh.phung.jy@renesas.com>
Signed-off-by: default avatarWolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210121110008.15894-2-wsa+renesas@sang-engineering.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent e8ac55a5

arch/arm64/boot/dts/renesas/r8a779a0.dtsi

+50 −0
Original line number Diff line number Diff line
@@ -663,11 +663,61 @@ scif0: serial@e6e60000 { 
				 <&cpg CPG_CORE R8A779A0_CLK_S1D2>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac1 0x51>, <&dmac1 0x50>;

			dma-names = "tx", "rx";

			power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;

			resets = <&cpg 702>;

			status = "disabled";

		};



		scif1: serial@e6e68000 {

			compatible = "renesas,scif-r8a779a0",

				     "renesas,rcar-gen3-scif", "renesas,scif";

			reg = <0 0xe6e68000 0 64>;

			interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 703>,

				 <&cpg CPG_CORE R8A779A0_CLK_S1D2>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac1 0x53>, <&dmac1 0x52>;

			dma-names = "tx", "rx";

			power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;

			resets = <&cpg 703>;

			status = "disabled";

		};



		scif3: serial@e6c50000 {

			compatible = "renesas,scif-r8a779a0",

				     "renesas,rcar-gen3-scif", "renesas,scif";

			reg = <0 0xe6c50000 0 64>;

			interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 704>,

				 <&cpg CPG_CORE R8A779A0_CLK_S1D2>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac1 0x57>, <&dmac1 0x56>;

			dma-names = "tx", "rx";

			power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;

			resets = <&cpg 704>;

			status = "disabled";

		};



		scif4: serial@e6c40000 {

			compatible = "renesas,scif-r8a779a0",

				     "renesas,rcar-gen3-scif", "renesas,scif";

			reg = <0 0xe6c40000 0 64>;

			interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 705>,

				 <&cpg CPG_CORE R8A779A0_CLK_S1D2>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac1 0x59>, <&dmac1 0x58>;

			dma-names = "tx", "rx";

			power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;

			resets = <&cpg 705>;

			status = "disabled";

		};



		msiof0: spi@e6e90000 {

			compatible = "renesas,msiof-r8a779a0",

				     "renesas,rcar-gen3-msiof";