Commit bcc6aa61 authored by Eryk Brol's avatar Eryk Brol Committed by Alex Deucher
Browse files

drm/amd/display: Fix DSC force enable on SST 



[why]
Previously when force enabling DSC on SST display we unknowingly
supressed lane count, which caused DSC to be enabled automatically.

[how]
By adding an additional flag to force enable DSC in dc_dsc.c DSC can
always be enabled with debugfs dsc_clock_en forced to 1

Cc: stable@vger.kernel.org
Signed-off-by: default avatarEryk Brol <eryk.brol@amd.com>
Signed-off-by: default avatarMikita Lipski <mikita.lipski@amd.com>
Reviewed-by: default avatarWenjing Liu <Wenjing.Liu@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 4bb23a54

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+3 −0
Original line number Diff line number Diff line
@@ -4646,6 +4646,9 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, 


#if defined(CONFIG_DRM_AMD_DC_DCN)

		if (dsc_caps.is_dsc_supported) {

			/* Set DSC policy according to dsc_clock_en */

			dc_dsc_policy_set_enable_dsc_when_not_needed(aconnector->dsc_settings.dsc_clock_en);



			if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],

						  &dsc_caps,

						  aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override,

drivers/gpu/drm/amd/display/dc/dc_dsc.h

+3 −0
Original line number Diff line number Diff line
@@ -51,6 +51,7 @@ struct dc_dsc_policy { 
	int min_slice_height; // Must not be less than 8

	uint32_t max_target_bpp;

	uint32_t min_target_bpp;

	bool enable_dsc_when_not_needed;

};



bool dc_dsc_parse_dsc_dpcd(const struct dc *dc,
@@ -80,4 +81,6 @@ void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing, 


void dc_dsc_policy_set_max_target_bpp_limit(uint32_t limit);



void dc_dsc_policy_set_enable_dsc_when_not_needed(bool enable);



#endif

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

+15 −1
Original line number Diff line number Diff line
@@ -34,6 +34,9 @@ 
/* default DSC policy target bitrate limit is 16bpp */

static uint32_t dsc_policy_max_target_bpp_limit = 16;



/* default DSC policy enables DSC only when needed */

static bool dsc_policy_enable_dsc_when_not_needed;



static uint32_t dc_dsc_bandwidth_in_kbps_from_timing(

	const struct dc_crtc_timing *timing)

{
@@ -360,7 +363,7 @@ static bool decide_dsc_target_bpp_x16( 


	get_dsc_bandwidth_range(policy->min_target_bpp, policy->max_target_bpp,

			dsc_common_caps, timing, &range);

	if (target_bandwidth_kbps >= range.stream_kbps) {

	if (!policy->enable_dsc_when_not_needed && target_bandwidth_kbps >= range.stream_kbps) {

		/* enough bandwidth without dsc */

		*target_bpp_x16 = 0;

		should_use_dsc = false;
@@ -961,9 +964,20 @@ void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing, struct dc 
	/* internal upper limit, default 16 bpp */

	if (policy->max_target_bpp > dsc_policy_max_target_bpp_limit)

		policy->max_target_bpp = dsc_policy_max_target_bpp_limit;



	/* enable DSC when not needed, default false */

	if (dsc_policy_enable_dsc_when_not_needed)

		policy->enable_dsc_when_not_needed = dsc_policy_enable_dsc_when_not_needed;

	else

		policy->enable_dsc_when_not_needed = false;

}



void dc_dsc_policy_set_max_target_bpp_limit(uint32_t limit)

{

	dsc_policy_max_target_bpp_limit = limit;

}



void dc_dsc_policy_set_enable_dsc_when_not_needed(bool enable)

{

	dsc_policy_enable_dsc_when_not_needed = enable;

}