Commit ba5e46f7 authored by Fabio Estevam's avatar Fabio Estevam Committed by Shawn Guo
Browse files

ARM: dts: imx7d-sdb: Allow UHS modes 



Describe the SD1_VSELECT pad, which is necessary to allow UHS modes.

Also, to support higher SD card speed modes, describe the 100MHz and
200MHz SD card pinctrl entries.

Suggested-by: default avatarYe Li <ye.li@nxp.com>
Signed-off-by: default avatarFabio Estevam <festevam@denx.de>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent dda66e99

arch/arm/boot/dts/imx7d-sdb.dts

+35 −5
Original line number Diff line number Diff line
@@ -484,8 +484,10 @@ &usbotg2 { 
};



&usdhc1 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_usdhc1>;

	pinctrl-names = "default", "state_100mhz", "state_200mhz";

	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;

	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;

	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;

	cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;

	wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;

	vmmc-supply = <&reg_sd1_vmmc>;
@@ -743,6 +745,15 @@ MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79 
			>;

		};



		pinctrl_usdhc1_gpio: usdhc1_gpiogrp {

			fsl,pins = <

				MX7D_PAD_SD1_CD_B__GPIO5_IO0		0x59 /* CD */

				MX7D_PAD_SD1_WP__GPIO5_IO1		0x59 /* WP */

				MX7D_PAD_SD1_RESET_B__GPIO5_IO2		0x59 /* vmmc */

				MX7D_PAD_GPIO1_IO08__SD1_VSELECT	0x59 /* VSELECT */

			>;

		};



		pinctrl_usdhc1: usdhc1grp {

			fsl,pins = <

				MX7D_PAD_SD1_CMD__SD1_CMD		0x59
@@ -751,9 +762,28 @@ MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 
				MX7D_PAD_SD1_DATA1__SD1_DATA1		0x59

				MX7D_PAD_SD1_DATA2__SD1_DATA2		0x59

				MX7D_PAD_SD1_DATA3__SD1_DATA3		0x59

				MX7D_PAD_SD1_CD_B__GPIO5_IO0		0x59 /* CD */

				MX7D_PAD_SD1_WP__GPIO5_IO1		0x59 /* WP */

				MX7D_PAD_SD1_RESET_B__GPIO5_IO2		0x59 /* vmmc */

			>;

		};



		pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {

			fsl,pins = <

				MX7D_PAD_SD1_CMD__SD1_CMD		0x5a

				MX7D_PAD_SD1_CLK__SD1_CLK		0x1a

				MX7D_PAD_SD1_DATA0__SD1_DATA0		0x5a

				MX7D_PAD_SD1_DATA1__SD1_DATA1		0x5a

				MX7D_PAD_SD1_DATA2__SD1_DATA2		0x5a

				MX7D_PAD_SD1_DATA3__SD1_DATA3		0x5a

			>;

		};



		pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {

			fsl,pins = <

				MX7D_PAD_SD1_CMD__SD1_CMD		0x5b

				MX7D_PAD_SD1_CLK__SD1_CLK		0x1b

				MX7D_PAD_SD1_DATA0__SD1_DATA0		0x5b

				MX7D_PAD_SD1_DATA1__SD1_DATA1		0x5b

				MX7D_PAD_SD1_DATA2__SD1_DATA2		0x5b

				MX7D_PAD_SD1_DATA3__SD1_DATA3		0x5b

			>;

		};