Merge tag 'tegra-for-5.17-dt-bindings' of... (b87cd375) · Commits · github.com / kvm-riscv / linux

Documentation/devicetree/bindings/arm/tegra.yaml

+39 −9

Original line number	Diff line number	Diff line
		@@ -36,6 +36,9 @@ properties:
		- toradex,colibri_t20-iris
		- const: toradex,colibri_t20
		- const: nvidia,tegra20
		- items:
		- const: asus,tf101
		- const: nvidia,tegra20
		- items:
		- const: acer,picasso
		- const: nvidia,tegra20
		@@ -49,6 +52,18 @@ properties:
		- nvidia,cardhu-a04
		- const: nvidia,cardhu
		- const: nvidia,tegra30
		- items:
		- const: asus,tf201
		- const: nvidia,tegra30
		- items:
		- const: asus,tf300t
		- const: nvidia,tegra30
		- items:
		- const: asus,tf300tg
		- const: nvidia,tegra30
		- items:
		- const: asus,tf700t
		- const: nvidia,tegra30
		- items:
		- const: toradex,apalis_t30-eval
		- const: toradex,apalis_t30
		@@ -74,8 +89,12 @@ properties:
		- items:
		- const: ouya,ouya
		- const: nvidia,tegra30
		- items:
		- const: pegatron,chagall
		- const: nvidia,tegra30
		- items:
		- enum:
		- asus,tf701t
		- nvidia,dalmore
		- nvidia,roth
		- nvidia,tn7
		@@ -108,14 +127,17 @@ properties:
		- nvidia,p2571
		- nvidia,p2894-0050-a08
		- const: nvidia,tegra210
		- items:
		- enum:
		- nvidia,p2771-0000
		- nvidia,p3509-0000+p3636-0001
		- description: Jetson TX2 Developer Kit
		items:
		- const: nvidia,p2771-0000
		- const: nvidia,tegra186
		- items:
		- enum:
		- nvidia,p2972-0000
		- description: Jetson TX2 NX Developer Kit
		items:
		- const: nvidia,p3509-0000+p3636-0001
		- const: nvidia,tegra186
		- description: Jetson AGX Xavier Developer Kit
		items:
		- const: nvidia,p2972-0000
		- const: nvidia,tegra194
		- description: Jetson Xavier NX
		items:
		@@ -134,8 +156,16 @@ properties:
		- const: nvidia,p3509-0000+p3668-0001
		- const: nvidia,tegra194
		- items:
		- enum:
		- nvidia,tegra234-vdk
		- const: nvidia,tegra234-vdk
		- const: nvidia,tegra234
		- description: Jetson AGX Orin
		items:
		- const: nvidia,p3701-0000
		- const: nvidia,tegra234
		- description: Jetson AGX Orin Developer Kit
		items:
		- const: nvidia,p3737-0000+p3701-0000
		- const: nvidia,p3701-0000
		- const: nvidia,tegra234

		additionalProperties: true

Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt

deleted100644 → 0

+0 −133

Original line number	Diff line number	Diff line
		NVIDIA Tegra Power Management Controller (PMC)

		Required properties:
		- compatible: Should contain one of the following:
		- "nvidia,tegra186-pmc": for Tegra186
		- "nvidia,tegra194-pmc": for Tegra194
		- "nvidia,tegra234-pmc": for Tegra234
		- reg: Must contain an (offset, length) pair of the register set for each
		entry in reg-names.
		- reg-names: Must include the following entries:
		- "pmc"
		- "wake"
		- "aotag"
		- "scratch"
		- "misc" (Only for Tegra194 and later)

		Optional properties:
		- nvidia,invert-interrupt: If present, inverts the PMU interrupt signal.
		- interrupt-controller: Identifies the node as an interrupt controller.
		- #interrupt-cells: Specifies the number of cells needed to encode an
		interrupt source. The value must be 2.

		Example:

		SoC DTSI:

		pmc@c3600000 {
		compatible = "nvidia,tegra186-pmc";
		reg = <0 0x0c360000 0 0x10000>,
		<0 0x0c370000 0 0x10000>,
		<0 0x0c380000 0 0x10000>,
		<0 0x0c390000 0 0x10000>;
		reg-names = "pmc", "wake", "aotag", "scratch";
		};

		Board DTS:

		pmc@c360000 {
		nvidia,invert-interrupt;
		};

		== Pad Control ==

		On Tegra SoCs a pad is a set of pins which are configured as a group.
		The pin grouping is a fixed attribute of the hardware. The PMC can be
		used to set pad power state and signaling voltage. A pad can be either
		in active or power down mode. The support for power state and signaling
		voltage configuration varies depending on the pad in question. 3.3 V and
		1.8 V signaling voltages are supported on pins where software
		controllable signaling voltage switching is available.

		Pad configurations are described with pin configuration nodes which
		are placed under the pmc node and they are referred to by the pinctrl
		client properties. For more information see
		Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt.

		The following pads are present on Tegra186:
		csia csib dsi mipi-bias
		pex-clk-bias pex-clk3 pex-clk2 pex-clk1
		usb0 usb1 usb2 usb-bias
		uart audio hsic dbg
		hdmi-dp0 hdmi-dp1 pex-cntrl sdmmc2-hv
		sdmmc4 cam dsib dsic
		dsid csic csid csie
		dsif spi ufs dmic-hv
		edp sdmmc1-hv sdmmc3-hv conn
		audio-hv ao-hv

		Required pin configuration properties:
		- pins: A list of strings, each of which contains the name of a pad
		to be configured.

		Optional pin configuration properties:
		- low-power-enable: Configure the pad into power down mode
		- low-power-disable: Configure the pad into active mode
		- power-source: Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
		TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages.
		The values are defined in
		include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h.

		Note: The power state can be configured on all of the above pads except
		for ao-hv. Following pads have software configurable signaling
		voltages: sdmmc2-hv, dmic-hv, sdmmc1-hv, sdmmc3-hv, audio-hv,
		ao-hv.

		Pad configuration state example:
		pmc: pmc@7000e400 {
		compatible = "nvidia,tegra186-pmc";
		reg = <0 0x0c360000 0 0x10000>,
		<0 0x0c370000 0 0x10000>,
		<0 0x0c380000 0 0x10000>,
		<0 0x0c390000 0 0x10000>;
		reg-names = "pmc", "wake", "aotag", "scratch";

		...

		sdmmc1_3v3: sdmmc1-3v3 {
		pins = "sdmmc1-hv";
		power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
		};

		sdmmc1_1v8: sdmmc1-1v8 {
		pins = "sdmmc1-hv";
		power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
		};

		hdmi_off: hdmi-off {
		pins = "hdmi";
		low-power-enable;
		}

		hdmi_on: hdmi-on {
		pins = "hdmi";
		low-power-disable;
		}
		};

		Pinctrl client example:
		sdmmc1: sdhci@3400000 {
		...
		pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
		pinctrl-0 = <&sdmmc1_3v3>;
		pinctrl-1 = <&sdmmc1_1v8>;
		};

		...

		sor0: sor@15540000 {
		...
		pinctrl-0 = <&hdmi_off>;
		pinctrl-1 = <&hdmi_on>;
		pinctrl-names = "hdmi-on", "hdmi-off";
		};

Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml

0 → 100644

+198 −0

Original line number	Diff line number	Diff line
		# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
		%YAML 1.2
		---
		$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml#
		$schema: http://devicetree.org/meta-schemas/core.yaml#

		title: NVIDIA Tegra Power Management Controller (PMC)

		maintainers:
		- Thierry Reding <thierry.reding@gmail.com>
		- Jon Hunter <jonathanh@nvidia.com>

		properties:
		compatible:
		enum:
		- nvidia,tegra186-pmc
		- nvidia,tegra194-pmc
		- nvidia,tegra234-pmc

		reg:
		minItems: 4
		maxItems: 5

		reg-names:
		minItems: 4
		items:
		- const: pmc
		- const: wake
		- const: aotag
		- const: scratch
		- const: misc

		interrupt-controller: true

		"#interrupt-cells":
		description: Specifies the number of cells needed to encode an
		interrupt source. The value must be 2.
		const: 2

		nvidia,invert-interrupt:
		description: If present, inverts the PMU interrupt signal.
		$ref: /schemas/types.yaml#/definitions/flag

		if:
		properties:
		compatible:
		contains:
		const: nvidia,tegra186-pmc
		then:
		properties:
		reg:
		maxItems: 4

		reg-names:
		maxItems: 4
		else:
		properties:
		reg:
		minItems: 5

		reg-names:
		minItems: 5

		patternProperties:
		"^[a-z0-9]+-[a-z0-9]+$":
		if:
		type: object
		then:
		description: \|
		These are pad configuration nodes. On Tegra SoCs a pad is a set of
		pins which are configured as a group. The pin grouping is a fixed
		attribute of the hardware. The PMC can be used to set pad power
		state and signaling voltage. A pad can be either in active or
		power down mode. The support for power state and signaling voltage
		configuration varies depending on the pad in question. 3.3 V and
		1.8 V signaling voltages are supported on pins where software
		controllable signaling voltage switching is available.

		Pad configurations are described with pin configuration nodes
		which are placed under the pmc node and they are referred to by
		the pinctrl client properties. For more information see

		Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt

		The following pads are present on Tegra186:

		csia, csib, dsi, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2,
		pex-clk1, usb0, usb1, usb2, usb-bias, uart, audio, hsic, dbg,
		hdmi-dp0, hdmi-dp1, pex-cntrl, sdmmc2-hv, sdmmc4, cam, dsib,
		dsic, dsid, csic, csid, csie, dsif, spi, ufs, dmic-hv, edp,
		sdmmc1-hv, sdmmc3-hv, conn, audio-hv, ao-hv

		The following pads are present on Tegra194:

		csia, csib, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2,
		pex-clk1, eqos, pex-clk-2-bias, pex-clk-2, dap3, dap5, uart,
		pwr-ctl, soc-gpio53, audio, gp-pwm2, gp-pwm3, soc-gpio12,
		soc-gpio13, soc-gpio10, uart4, uart5, dbg, hdmi-dp3, hdmi-dp2,
		hdmi-dp0, hdmi-dp1, pex-cntrl, pex-ctl2, pex-l0-rst,
		pex-l1-rst, sdmmc4, pex-l5-rst, cam, csic, csid, csie, csif,
		spi, ufs, csig, csih, edp, sdmmc1-hv, sdmmc3-hv, conn,
		audio-hv, ao-hv

		properties:
		pins:
		$ref: /schemas/types.yaml#/definitions/string
		description: Must contain the name of the pad(s) to be
		configured.

		low-power-enable:
		description: Configure the pad into power down mode.
		$ref: /schemas/types.yaml#/definitions/flag

		low-power-disable:
		description: Configure the pad into active mode.
		$ref: /schemas/types.yaml#/definitions/flag

		power-source:
		$ref: /schemas/types.yaml#/definitions/uint32
		description: \|
		Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
		TEGRA_IO_PAD_VOLTAGE_3V3 to select between signalling
		voltages.

		The values are defined in

		include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h

		The power state can be configured on all of the above pads
		except for ao-hv. Following pads have software configurable
		signaling voltages: sdmmc2-hv, dmic-hv, sdmmc1-hv, sdmmc3-hv,
		audio-hv, ao-hv.

		phandle: true

		required:
		- pins

		additionalProperties: false

		required:
		- compatible
		- reg
		- reg-names

		additionalProperties: false

		dependencies:
		interrupt-controller: ['#interrupt-cells']
		"#interrupt-cells":
		required:
		- interrupt-controller

		examples:
		- \|
		#include <dt-bindings/clock/tegra186-clock.h>
		#include <dt-bindings/interrupt-controller/arm-gic.h>
		#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
		#include <dt-bindings/memory/tegra186-mc.h>
		#include <dt-bindings/reset/tegra186-reset.h>

		pmc@c3600000 {
		compatible = "nvidia,tegra186-pmc";
		reg = <0x0c360000 0x10000>,
		<0x0c370000 0x10000>,
		<0x0c380000 0x10000>,
		<0x0c390000 0x10000>;
		reg-names = "pmc", "wake", "aotag", "scratch";
		nvidia,invert-interrupt;

		sdmmc1_3v3: sdmmc1-3v3 {
		pins = "sdmmc1-hv";
		power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
		};

		sdmmc1_1v8: sdmmc1-1v8 {
		pins = "sdmmc1-hv";
		power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
		};
		};

		sdmmc1: mmc@3400000 {
		compatible = "nvidia,tegra186-sdhci";
		reg = <0x03400000 0x10000>;
		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
		<&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
		clock-names = "sdhci", "tmclk";
		resets = <&bpmp TEGRA186_RESET_SDMMC1>;
		reset-names = "sdhci";
		interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>,
		<&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>;
		interconnect-names = "dma-mem", "write";
		iommus = <&smmu TEGRA186_SID_SDMMC1>;
		pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
		pinctrl-0 = <&sdmmc1_3v3>;
		pinctrl-1 = <&sdmmc1_1v8>;
		};

Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml

+37 −0

Original line number	Diff line number	Diff line
		@@ -42,6 +42,36 @@ properties:
		"#reset-cells":
		const: 1

		patternProperties:
		"^(sclk)\|(pll-[cem])$":
		type: object
		properties:
		compatible:
		enum:
		- nvidia,tegra20-sclk
		- nvidia,tegra30-sclk
		- nvidia,tegra30-pllc
		- nvidia,tegra30-plle
		- nvidia,tegra30-pllm

		operating-points-v2: true

		clocks:
		items:
		- description: node's clock

		power-domains:
		maxItems: 1
		description: phandle to the core SoC power domain

		required:
		- compatible
		- operating-points-v2
		- clocks
		- power-domains

		additionalProperties: false

		required:
		- compatible
		- reg
		@@ -59,6 +89,13 @@ examples:
		reg = <0x60006000 0x1000>;
		#clock-cells = <1>;
		#reset-cells = <1>;

		sclk {
		compatible = "nvidia,tegra20-sclk";
		operating-points-v2 = <&opp_table>;
		clocks = <&tegra_car TEGRA20_CLK_SCLK>;
		power-domains = <&domain>;
		};
		};

		usb-controller@c5004000 {

Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt

+53 −0

Original line number	Diff line number	Diff line
		@@ -19,6 +19,19 @@ Required properties:
		See ../reset/reset.txt for details.
		- reset-names: Must include the following entries:
		- host1x
		- mc

		Optional properties:
		- operating-points-v2: See ../bindings/opp/opp.txt for details.
		- power-domains: Phandle to HEG or core power domain.

		For each opp entry in 'operating-points-v2' table of host1x and its modules:
		- opp-supported-hw: One bitfield indicating:
		On Tegra20: SoC process ID mask
		On Tegra30+: SoC speedo ID mask

		A bitwise AND is performed against the value and if any bit
		matches, the OPP gets enabled.

		Each host1x client module having to perform DMA through the Memory Controller
		should have the interconnect endpoints set to the Memory Client and External
		@@ -45,6 +58,8 @@ of the following host1x client modules:
		- interconnect-names: Must include name of the interconnect path for each
		interconnect entry. Consult TRM documentation for information about
		available memory clients, see MEMORY CONTROLLER section.
		- operating-points-v2: See ../bindings/opp/opp.txt for details.
		- power-domains: Phandle to MPE power domain.

		- vi: video input

		@@ -128,6 +143,8 @@ of the following host1x client modules:
		- interconnect-names: Must include name of the interconnect path for each
		interconnect entry. Consult TRM documentation for information about
		available memory clients, see MEMORY CONTROLLER section.
		- operating-points-v2: See ../bindings/opp/opp.txt for details.
		- power-domains: Phandle to VENC power domain.

		- epp: encoder pre-processor

		@@ -147,6 +164,8 @@ of the following host1x client modules:
		- interconnect-names: Must include name of the interconnect path for each
		interconnect entry. Consult TRM documentation for information about
		available memory clients, see MEMORY CONTROLLER section.
		- operating-points-v2: See ../bindings/opp/opp.txt for details.
		- power-domains: Phandle to HEG or core power domain.

		- isp: image signal processor

		@@ -166,6 +185,7 @@ of the following host1x client modules:
		- interconnect-names: Must include name of the interconnect path for each
		interconnect entry. Consult TRM documentation for information about
		available memory clients, see MEMORY CONTROLLER section.
		- power-domains: Phandle to VENC or core power domain.

		- gr2d: 2D graphics engine

		@@ -179,12 +199,15 @@ of the following host1x client modules:
		See ../reset/reset.txt for details.
		- reset-names: Must include the following entries:
		- 2d
		- mc

		Optional properties:
		- interconnects: Must contain entry for the GR2D memory clients.
		- interconnect-names: Must include name of the interconnect path for each
		interconnect entry. Consult TRM documentation for information about
		available memory clients, see MEMORY CONTROLLER section.
		- operating-points-v2: See ../bindings/opp/opp.txt for details.
		- power-domains: Phandle to HEG or core power domain.

		- gr3d: 3D graphics engine

		@@ -203,12 +226,16 @@ of the following host1x client modules:
		- reset-names: Must include the following entries:
		- 3d
		- 3d2 (Only required on SoCs with two 3D clocks)
		- mc
		- mc2 (Only required on SoCs with two 3D clocks)

		Optional properties:
		- interconnects: Must contain entry for the GR3D memory clients.
		- interconnect-names: Must include name of the interconnect path for each
		interconnect entry. Consult TRM documentation for information about
		available memory clients, see MEMORY CONTROLLER section.
		- operating-points-v2: See ../bindings/opp/opp.txt for details.
		- power-domains: Phandles to 3D or core power domain.

		- dc: display controller

		@@ -241,6 +268,8 @@ of the following host1x client modules:
		- interconnect-names: Must include name of the interconnect path for each
		interconnect entry. Consult TRM documentation for information about
		available memory clients, see MEMORY CONTROLLER section.
		- operating-points-v2: See ../bindings/opp/opp.txt for details.
		- power-domains: Phandle to core power domain.

		- hdmi: High Definition Multimedia Interface

		@@ -267,6 +296,7 @@ of the following host1x client modules:
		- nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
		- nvidia,edid: supplies a binary EDID blob
		- nvidia,panel: phandle of a display panel
		- operating-points-v2: See ../bindings/opp/opp.txt for details.

		- tvo: TV encoder output

		@@ -277,6 +307,10 @@ of the following host1x client modules:
		- clocks: Must contain one entry, for the module clock.
		See ../clocks/clock-bindings.txt for details.

		Optional properties:
		- operating-points-v2: See ../bindings/opp/opp.txt for details.
		- power-domains: Phandle to core power domain.

		- dsi: display serial interface

		Required properties:
		@@ -305,6 +339,7 @@ of the following host1x client modules:
		- nvidia,panel: phandle of a display panel
		- nvidia,ganged-mode: contains a phandle to a second DSI controller to gang
		up with in order to support up to 8 data lanes
		- operating-points-v2: See ../bindings/opp/opp.txt for details.

		- sor: serial output resource

		@@ -408,6 +443,8 @@ Example:
		clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
		resets = <&tegra_car 28>;
		reset-names = "host1x";
		operating-points-v2 = <&dvfs_opp_table>;
		power-domains = <&domain>;

		#address-cells = <1>;
		#size-cells = <1>;
		@@ -421,6 +458,8 @@ Example:
		clocks = <&tegra_car TEGRA20_CLK_MPE>;
		resets = <&tegra_car 60>;
		reset-names = "mpe";
		operating-points-v2 = <&dvfs_opp_table>;
		power-domains = <&domain>;
		};

		vi@54080000 {
		@@ -429,6 +468,7 @@ Example:
		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
		assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
		assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
		operating-points-v2 = <&dvfs_opp_table>;

		clocks = <&tegra_car TEGRA210_CLK_VI>;
		power-domains = <&pd_venc>;
		@@ -510,6 +550,8 @@ Example:
		clocks = <&tegra_car TEGRA20_CLK_EPP>;
		resets = <&tegra_car 19>;
		reset-names = "epp";
		operating-points-v2 = <&dvfs_opp_table>;
		power-domains = <&domain>;
		};

		isp {
		@@ -528,6 +570,8 @@ Example:
		clocks = <&tegra_car TEGRA20_CLK_GR2D>;
		resets = <&tegra_car 21>;
		reset-names = "2d";
		operating-points-v2 = <&dvfs_opp_table>;
		power-domains = <&domain>;
		};

		gr3d {
		@@ -536,6 +580,8 @@ Example:
		clocks = <&tegra_car TEGRA20_CLK_GR3D>;
		resets = <&tegra_car 24>;
		reset-names = "3d";
		operating-points-v2 = <&dvfs_opp_table>;
		power-domains = <&domain>;
		};

		dc@54200000 {
		@@ -547,6 +593,8 @@ Example:
		clock-names = "dc", "parent";
		resets = <&tegra_car 27>;
		reset-names = "dc";
		operating-points-v2 = <&dvfs_opp_table>;
		power-domains = <&domain>;

		interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>,
		<&mc TEGRA20_MC_DISPLAY0B &emc>,
		@@ -571,6 +619,8 @@ Example:
		clock-names = "dc", "parent";
		resets = <&tegra_car 26>;
		reset-names = "dc";
		operating-points-v2 = <&dvfs_opp_table>;
		power-domains = <&domain>;

		interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>,
		<&mc TEGRA20_MC_DISPLAY0BB &emc>,
		@@ -596,6 +646,7 @@ Example:
		resets = <&tegra_car 51>;
		reset-names = "hdmi";
		status = "disabled";
		operating-points-v2 = <&dvfs_opp_table>;
		};

		tvo {
		@@ -604,6 +655,7 @@ Example:
		interrupts = <0 76 0x04>;
		clocks = <&tegra_car TEGRA20_CLK_TVO>;
		status = "disabled";
		operating-points-v2 = <&dvfs_opp_table>;
		};

		dsi {
		@@ -615,6 +667,7 @@ Example:
		resets = <&tegra_car 48>;
		reset-names = "dsi";
		status = "disabled";
		operating-points-v2 = <&dvfs_opp_table>;
		};
		};