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Commit b6768530 authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
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clk: renesas: r9a07g043: Add TSU clock and reset entry 



Add TSU clock and reset entry to CPG driver.

Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220501083450.26541-4-biju.das.jz@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 14d8857d
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