Commit b5de1a9f authored by Bhupesh Sharma's avatar Bhupesh Sharma Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: sm6115: Add CPU idle-states 



Add CPU idle-state nodes and power-domains in Qualcomm sm6115 SoC dtsi.

Signed-off-by: default avatarBhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230518080031.2509250-1-bhupesh.sharma@linaro.org
parent 8bbd3577

arch/arm64/boot/dts/qcom/sm6115.dtsi

+136 −0
Original line number Diff line number Diff line
@@ -47,6 +47,8 @@ CPU0: cpu@0 { 
			enable-method = "psci";

			next-level-cache = <&L2_0>;

			qcom,freq-domain = <&cpufreq_hw 0>;

			power-domains = <&CPU_PD0>;

			power-domain-names = "psci";

			L2_0: l2-cache {

				compatible = "cache";

				cache-level = <2>;
@@ -63,6 +65,8 @@ CPU1: cpu@1 { 
			enable-method = "psci";

			next-level-cache = <&L2_0>;

			qcom,freq-domain = <&cpufreq_hw 0>;

			power-domains = <&CPU_PD1>;

			power-domain-names = "psci";

		};



		CPU2: cpu@2 {
@@ -75,6 +79,8 @@ CPU2: cpu@2 { 
			enable-method = "psci";

			next-level-cache = <&L2_0>;

			qcom,freq-domain = <&cpufreq_hw 0>;

			power-domains = <&CPU_PD2>;

			power-domain-names = "psci";

		};



		CPU3: cpu@3 {
@@ -87,6 +93,8 @@ CPU3: cpu@3 { 
			enable-method = "psci";

			next-level-cache = <&L2_0>;

			qcom,freq-domain = <&cpufreq_hw 0>;

			power-domains = <&CPU_PD3>;

			power-domain-names = "psci";

		};



		CPU4: cpu@100 {
@@ -99,6 +107,8 @@ CPU4: cpu@100 { 
			dynamic-power-coefficient = <282>;

			next-level-cache = <&L2_1>;

			qcom,freq-domain = <&cpufreq_hw 1>;

			power-domains = <&CPU_PD4>;

			power-domain-names = "psci";

			L2_1: l2-cache {

				compatible = "cache";

				cache-level = <2>;
@@ -115,6 +125,8 @@ CPU5: cpu@101 { 
			enable-method = "psci";

			next-level-cache = <&L2_1>;

			qcom,freq-domain = <&cpufreq_hw 1>;

			power-domains = <&CPU_PD5>;

			power-domain-names = "psci";

		};



		CPU6: cpu@102 {
@@ -127,6 +139,8 @@ CPU6: cpu@102 { 
			enable-method = "psci";

			next-level-cache = <&L2_1>;

			qcom,freq-domain = <&cpufreq_hw 1>;

			power-domains = <&CPU_PD6>;

			power-domain-names = "psci";

		};



		CPU7: cpu@103 {
@@ -139,6 +153,8 @@ CPU7: cpu@103 { 
			enable-method = "psci";

			next-level-cache = <&L2_1>;

			qcom,freq-domain = <&cpufreq_hw 1>;

			power-domains = <&CPU_PD7>;

			power-domain-names = "psci";

		};



		cpu-map {
@@ -178,6 +194,68 @@ core3 { 
				};

			};

		};



		idle-states {

			entry-method = "psci";



			LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {

				compatible = "arm,idle-state";

				idle-state-name = "silver-rail-power-collapse";

				arm,psci-suspend-param = <0x40000003>;

				entry-latency-us = <290>;

				exit-latency-us = <376>;

				min-residency-us = <1182>;

				local-timer-stop;

			};



			BIG_CPU_SLEEP_0: cpu-sleep-1-0 {

				compatible = "arm,idle-state";

				idle-state-name = "gold-rail-power-collapse";

				arm,psci-suspend-param = <0x40000003>;

				entry-latency-us = <297>;

				exit-latency-us = <324>;

				min-residency-us = <1110>;

				local-timer-stop;

			};

		};



		domain-idle-states {

			CLUSTER_0_SLEEP_0: cluster-sleep-0-0 {

				/* GDHS */

				compatible = "domain-idle-state";

				arm,psci-suspend-param = <0x40000022>;

				entry-latency-us = <360>;

				exit-latency-us = <421>;

				min-residency-us = <782>;

			};



			CLUSTER_0_SLEEP_1: cluster-sleep-0-1 {

				/* Power Collapse */

				compatible = "domain-idle-state";

				arm,psci-suspend-param = <0x41000044>;

				entry-latency-us = <800>;

				exit-latency-us = <2118>;

				min-residency-us = <7376>;

			};



			CLUSTER_1_SLEEP_0: cluster-sleep-1-0 {

				/* GDHS */

				compatible = "domain-idle-state";

				arm,psci-suspend-param = <0x40000042>;

				entry-latency-us = <314>;

				exit-latency-us = <345>;

				min-residency-us = <660>;

			};



			CLUSTER_1_SLEEP_1: cluster-sleep-1-1 {

				/* Power Collapse */

				compatible = "domain-idle-state";

				arm,psci-suspend-param = <0x41000044>;

				entry-latency-us = <640>;

				exit-latency-us = <1654>;

				min-residency-us = <8094>;

			};

		};

	};



	firmware {
@@ -201,6 +279,64 @@ pmu { 
	psci {

		compatible = "arm,psci-1.0";

		method = "smc";



		CPU_PD0: power-domain-cpu0 {

			#power-domain-cells = <0>;

			power-domains = <&CLUSTER_0_PD>;

			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;

		};



		CPU_PD1: power-domain-cpu1 {

			#power-domain-cells = <0>;

			power-domains = <&CLUSTER_0_PD>;

			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;

		};



		CPU_PD2: power-domain-cpu2 {

			#power-domain-cells = <0>;

			power-domains = <&CLUSTER_0_PD>;

			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;

		};



		CPU_PD3: power-domain-cpu3 {

			#power-domain-cells = <0>;

			power-domains = <&CLUSTER_0_PD>;

			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;

		};



		CPU_PD4: power-domain-cpu4 {

			#power-domain-cells = <0>;

			power-domains = <&CLUSTER_1_PD>;

			domain-idle-states = <&BIG_CPU_SLEEP_0>;

		};



		CPU_PD5: power-domain-cpu5 {

			#power-domain-cells = <0>;

			power-domains = <&CLUSTER_1_PD>;

			domain-idle-states = <&BIG_CPU_SLEEP_0>;

		};



		CPU_PD6: power-domain-cpu6 {

			#power-domain-cells = <0>;

			power-domains = <&CLUSTER_1_PD>;

			domain-idle-states = <&BIG_CPU_SLEEP_0>;

		};



		CPU_PD7: power-domain-cpu7 {

			#power-domain-cells = <0>;

			power-domains = <&CLUSTER_1_PD>;

			domain-idle-states = <&BIG_CPU_SLEEP_0>;

		};



		CLUSTER_0_PD: power-domain-cpu-cluster0 {

			#power-domain-cells = <0>;

			domain-idle-states = <&CLUSTER_0_SLEEP_0>, <&CLUSTER_0_SLEEP_1>;

		};



		CLUSTER_1_PD: power-domain-cpu-cluster1 {

			#power-domain-cells = <0>;

			domain-idle-states = <&CLUSTER_1_SLEEP_0>, <&CLUSTER_1_SLEEP_1>;

		};

	};



	reserved_memory: reserved-memory {