Unverified Commit ab2dad6f authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'socfpga_dts_update_for_v5.18_part1' of... 

Merge tag 'socfpga_dts_update_for_v5.18_part1' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/dt

SoCFPGA dts updates for v5.18, part 1
- Cleanup of Altera/Intel ARMv7 and ARMv8 DTS and bindings

* tag 'socfpga_dts_update_for_v5.18_part1' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: (22 commits)
  ARM: dts: socfpga: cyclone5: align regulator node with dtschema
  ARM: dts: socfpga: arria10: align regulator node with dtschema
  arm64: dts: agilex: align pl330 node name with dtschema
  arm64: dts: stratix10: align pl330 node name with dtschema
  arm64: dts: intel: socfpga_agilex_socdk: align LED node names with dtschema
  arm64: dts: agilex: align mmc node names with dtschema
  arm64: dts: agilex: add board compatible for N5X DK
  arm64: dts: agilex: add board compatible for SoCFPGA DK
  arm64: dts: stratix10: align regulator node names with dtschema
  arm64: dts: stratix10: align mmc node names with dtschema
  arm64: dts: stratix10: move ARM timer out of SoC node
  arm64: dts: stratix10: add board compatible for SoCFPGA DK
  ARM: dts: arria10: add board compatible for SoCFPGA DK
  ARM: dts: arria10: add board compatible for Mercury AA1
  ARM: dts: arria5: add board compatible for SoCFPGA DK
  dt-bindings: clock: intel,stratix10: convert to dtschema
  dt-bindings: intel: document Agilex based board compatibles
  dt-bindings: altera: document Stratix 10 based board compatibles
  dt-bindings: altera: document VT compatibles
  dt-bindings: altera: document Arria 10 based board compatibles
  ...

Link: https://lore.kernel.org/r/20220211112556.98940-1-dinguyen@kernel.org


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 7e2d8a61 0f7b7151

Documentation/devicetree/bindings/arm/altera.yaml

+40 −6
Original line number Diff line number Diff line
@@ -13,11 +13,45 @@ properties: 
  $nodename:

    const: "/"

  compatible:

    oneOf:

      - description: Arria 5 boards

        items:

          - enum:

          - altr,socfpga-cyclone5

          - altr,socfpga-arria5

          - altr,socfpga-arria10

              - altr,socfpga-arria5-socdk

          - const: altr,socfpga-arria5

          - const: altr,socfpga



      - description: Arria 10 boards

        items:

          - enum:

              - altr,socfpga-arria10-socdk

              - enclustra,mercury-aa1

          - const: altr,socfpga-arria10

          - const: altr,socfpga



      - description: Cyclone 5 boards

        items:

          - enum:

              - altr,socfpga-cyclone5-socdk

              - denx,mcvevk

              - ebv,socrates

              - macnica,sodia

              - novtech,chameleon96

              - samtec,vining

              - terasic,de0-atlas

              - terasic,socfpga-cyclone5-sockit

          - const: altr,socfpga-cyclone5

          - const: altr,socfpga



      - description: Stratix 10 boards

        items:

          - enum:

              - altr,socfpga-stratix10-socdk

          - const: altr,socfpga-stratix10



      - description: SoCFPGA VT

        items:

          - const: altr,socfpga-vt

          - const: altr,socfpga



additionalProperties: true

Documentation/devicetree/bindings/arm/intel,socfpga.yaml

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+26 −0
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/arm/intel,socfpga.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Intel SoCFPGA platform device tree bindings



maintainers:

  - Dinh Nguyen <dinguyen@kernel.org>



properties:

  $nodename:

    const: "/"

  compatible:

    oneOf:

      - description: AgileX boards

        items:

          - enum:

              - intel,n5x-socdk

              - intel,socfpga-agilex-socdk

          - const: intel,socfpga-agilex



additionalProperties: true



...

Documentation/devicetree/bindings/clock/intc_stratix10.txt

deleted100644 → 0
+0 −20
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Device Tree Clock bindings for Intel's SoCFPGA Stratix10 platform



This binding uses the common clock binding[1].



[1] Documentation/devicetree/bindings/clock/clock-bindings.txt



Required properties:

- compatible : shall be

	"intel,stratix10-clkmgr"



- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.



- #clock-cells : from common clock binding, shall be set to 1.



Example:

	clkmgr: clock-controller@ffd10000 {

		compatible = "intel,stratix10-clkmgr";

		reg = <0xffd10000 0x1000>;

		#clock-cells = <1>;

	};

Documentation/devicetree/bindings/clock/intel,stratix10.yaml

0 → 100644
+35 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/intel,stratix10.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Intel SoCFPGA Stratix10 platform clock controller binding



maintainers:

  - Dinh Nguyen <dinguyen@kernel.org>



properties:

  compatible:

    const: intel,stratix10-clkmgr



  '#clock-cells':

    const: 1



  reg:

    maxItems: 1



required:

  - compatible

  - reg

  - '#clock-cells'



additionalProperties: false



examples:

  - |

    clock-controller@ffd10000 {

        compatible = "intel,stratix10-clkmgr";

        reg = <0xffd10000 0x1000>;

        #clock-cells = <1>;

    };

arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts

+1 −1
Original line number Diff line number Diff line
@@ -6,7 +6,7 @@ 
/ {



	model = "Enclustra Mercury AA1";

	compatible = "altr,socfpga-arria10", "altr,socfpga";

	compatible = "enclustra,mercury-aa1", "altr,socfpga-arria10", "altr,socfpga";



	aliases {

		ethernet0 = &gmac0;