Unverified Commit 7e2d8a61 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'samsung-dt64-5.18' of... 

Merge tag 'samsung-dt64-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt

Samsung DTS ARM64 changes for v5.18

1. Minor improvements and dtschema fixes (node names, properties).
2. Fix issues pointed out by DT schema checks:
 - Add necessary clock controller inputs on Exynos7.
 - Add USB DWC3 supplies.
 - Drop old syscon phandle on Exynos5433.
3. Add initial Exynos850 support and WinLink E850-96 board using it.

* tag 'samsung-dt64-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  arm64: dts: exynos: adjust USB DRD clocks with dtschema in Exynos7
  arm64: dts: exynos: drop unneeded syscon phandle in Exynos5433 LPASS
  arm64: dts: exynos: align pl330 node name with dtschema
  arm64: dts: exynos: Add initial E850-96 board support
  arm64: dts: exynos: Add initial Exynos850 SoC support
  arm64: dts: exynos: add USB DWC3 supplies to Espresso board
  arm64: dts: exynos: add necessary clock inputs in Exynos7
  arm64: dts: exynos: Align MAX77843 nodes with dtschema on TM2

Link: https://lore.kernel.org/r/20220209145226.184375-2-krzysztof.kozlowski@canonical.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 76990b47 a0d54553

arch/arm64/boot/dts/exynos/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -3,4 +3,5 @@ dtb-$(CONFIG_ARCH_EXYNOS) += \ 
	exynos5433-tm2.dtb	\

	exynos5433-tm2e.dtb	\

	exynos7-espresso.dtb	\

	exynos850-e850-96.dtb	\

	exynosautov9-sadk.dtb

arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi

+14 −3
Original line number Diff line number Diff line
@@ -858,10 +858,10 @@ pmic@66 { 
		interrupts = <5 IRQ_TYPE_EDGE_FALLING>;

		reg = <0x66>;



		muic: max77843-muic {

		muic: extcon {

			compatible = "maxim,max77843-muic";



			musb_con: musb-connector {

			musb_con: connector {

				compatible = "samsung,usb-connector-11pin",

					     "usb-b-connector";

				label = "micro-USB";
@@ -871,6 +871,17 @@ ports { 
					#address-cells = <1>;

					#size-cells = <0>;



					port@0 {

						/*

						 * TODO: The DTS this is based on does not have

						 * port@0 which is a required property. The ports

						 * look incomplete and need fixing.

						 * Add a disabled port just to satisfy dtschema.

						 */

						reg = <0>;

						status = "disabled";

					};



					port@3 {

						reg = <3>;

						musb_con_to_mhl: endpoint {
@@ -910,7 +921,7 @@ charger_reg: CHARGER { 
			};

		};



		haptic: max77843-haptic {

		haptic: motor-driver {

			compatible = "maxim,max77843-haptic";

			haptic-supply = <&ldo38_reg>;

			pwms = <&pwm 0 33670 0>;

arch/arm64/boot/dts/exynos/exynos5433.dtsi

+3 −4
Original line number Diff line number Diff line
@@ -1858,7 +1858,7 @@ mshc_2: mshc@15560000 { 
			status = "disabled";

		};



		pdma0: pdma@15610000 {

		pdma0: dma-controller@15610000 {

			compatible = "arm,pl330", "arm,primecell";

			reg = <0x15610000 0x1000>;

			interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
@@ -1869,7 +1869,7 @@ pdma0: pdma@15610000 { 
			#dma-requests = <32>;

		};



		pdma1: pdma@15600000 {

		pdma1: dma-controller@15600000 {

			compatible = "arm,pl330", "arm,primecell";

			reg = <0x15600000 0x1000>;

			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
@@ -1885,13 +1885,12 @@ audio-subsystem@11400000 { 
			reg = <0x11400000 0x100>, <0x11500000 0x08>;

			clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>;

			clock-names = "sfr0_ctrl";

			samsung,pmu-syscon = <&pmu_system_controller>;

			power-domains = <&pd_aud>;

			#address-cells = <1>;

			#size-cells = <1>;

			ranges;



			adma: adma@11420000 {

			adma: dma-controller@11420000 {

				compatible = "arm,pl330", "arm,primecell";

				reg = <0x11420000 0x1000>;

				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;

arch/arm64/boot/dts/exynos/exynos7-espresso.dts

+5 −0
Original line number Diff line number Diff line
@@ -412,6 +412,11 @@ &ufs { 
	status = "okay";

};



&usbdrd {

	vdd10-supply = <&ldo4_reg>;

	vdd33-supply = <&ldo6_reg>;

};



&usbdrd_phy {

	vbus-supply = <&usb30_vbus_reg>;

	vbus-boost-supply = <&usb3drd_boost_5v>;

arch/arm64/boot/dts/exynos/exynos7.dtsi

+32 −12
Original line number Diff line number Diff line
@@ -142,7 +142,7 @@ gic: interrupt-controller@11001000 { 
				<0x11006000 0x2000>;

		};



		pdma0: pdma@10e10000 {

		pdma0: dma-controller@10e10000 {

			compatible = "arm,pl330", "arm,primecell";

			reg = <0x10E10000 0x1000>;

			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
@@ -153,7 +153,7 @@ pdma0: pdma@10e10000 { 
			#dma-requests = <32>;

		};



		pdma1: pdma@10eb0000 {

		pdma1: dma-controller@10eb0000 {

			compatible = "arm,pl330", "arm,primecell";

			reg = <0x10EB0000 0x1000>;

			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
@@ -177,10 +177,11 @@ clock_top0: clock-controller@105d0000 { 
			clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,

				 <&clock_topc DOUT_SCLK_BUS1_PLL>,

				 <&clock_topc DOUT_SCLK_CC_PLL>,

				 <&clock_topc DOUT_SCLK_MFC_PLL>;

				 <&clock_topc DOUT_SCLK_MFC_PLL>,

				 <&clock_topc DOUT_SCLK_AUD_PLL>;

			clock-names = "fin_pll", "dout_sclk_bus0_pll",

				      "dout_sclk_bus1_pll", "dout_sclk_cc_pll",

				      "dout_sclk_mfc_pll";

				      "dout_sclk_mfc_pll", "dout_sclk_aud_pll";

		};



		clock_top1: clock-controller@105e0000 {
@@ -218,12 +219,32 @@ clock_peric1: clock-controller@14c80000 { 
			compatible = "samsung,exynos7-clock-peric1";

			reg = <0x14c80000 0xd00>;

			#clock-cells = <1>;

			clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>,

			clocks = <&fin_pll>,

				 <&clock_top0 DOUT_ACLK_PERIC1>,

				 <&clock_top0 CLK_SCLK_UART1>,

				 <&clock_top0 CLK_SCLK_UART2>,

				 <&clock_top0 CLK_SCLK_UART3>;

			clock-names = "fin_pll", "dout_aclk_peric1_66",

				      "sclk_uart1", "sclk_uart2", "sclk_uart3";

				 <&clock_top0 CLK_SCLK_UART3>,

				 <&clock_top0 CLK_SCLK_SPI0>,

				 <&clock_top0 CLK_SCLK_SPI1>,

				 <&clock_top0 CLK_SCLK_SPI2>,

				 <&clock_top0 CLK_SCLK_SPI3>,

				 <&clock_top0 CLK_SCLK_SPI4>,

				 <&clock_top0 CLK_SCLK_I2S1>,

				 <&clock_top0 CLK_SCLK_PCM1>,

				 <&clock_top0 CLK_SCLK_SPDIF>;

			clock-names = "fin_pll",

				      "dout_aclk_peric1_66",

				      "sclk_uart1",

				      "sclk_uart2",

				      "sclk_uart3",

				      "sclk_spi0",

				      "sclk_spi1",

				      "sclk_spi2",

				      "sclk_spi3",

				      "sclk_spi4",

				      "sclk_i2s1",

				      "sclk_pcm1",

				      "sclk_spdif";

		};



		clock_peris: clock-controller@10040000 {
@@ -663,16 +684,15 @@ usbdrd_phy: phy@15500000 { 
			reg = <0x15500000 0x100>;

			clocks = <&clock_fsys0 ACLK_USBDRD300>,

			       <&clock_fsys0 OSCCLK_PHY_CLKOUT_USB30_PHY>,

			       <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER>,

			       <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PHYCLK_USER>,

			       <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER>,

			       <&clock_fsys0 SCLK_USBDRD300_REFCLK>;

			clock-names = "phy", "ref", "phy_pipe",

				"phy_utmi", "itp";

			clock-names = "phy", "ref", "phy_utmi", "phy_pipe", "itp";

			samsung,pmu-syscon = <&pmu_system_controller>;

			#phy-cells = <1>;

		};



		usbdrd3 {

		usbdrd: usb {

			compatible = "samsung,exynos7-dwusb3";

			clocks = <&clock_fsys0 ACLK_USBDRD300>,

			       <&clock_fsys0 SCLK_USBDRD300_SUSPENDCLK>,