Commit a9379097 authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Geert Uytterhoeven
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ARM: dts: r8a7742: Add VSP support 



Add VSP support to R8A7742 (RZ/G1H) SoC dtsi.

Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: default avatarChris Paterson <Chris.Paterson2@renesas.com>
Link: https://lore.kernel.org/r/20200911080929.15058-1-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent c3d91c82

arch/arm/boot/dts/r8a7742.dtsi

+36 −0
Original line number Diff line number Diff line
@@ -1686,6 +1686,42 @@ pciec: pcie@fe000000 { 
			status = "disabled";

		};



		vsp@fe920000 {

			compatible = "renesas,vsp1";

			reg = <0 0xfe920000 0 0x8000>;

			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 130>;

			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;

			resets = <&cpg 130>;

		};



		vsp@fe928000 {

			compatible = "renesas,vsp1";

			reg = <0 0xfe928000 0 0x8000>;

			interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 131>;

			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;

			resets = <&cpg 131>;

		};



		vsp@fe930000 {

			compatible = "renesas,vsp1";

			reg = <0 0xfe930000 0 0x8000>;

			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 128>;

			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;

			resets = <&cpg 128>;

		};



		vsp@fe938000 {

			compatible = "renesas,vsp1";

			reg = <0 0xfe938000 0 0x8000>;

			interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 127>;

			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;

			resets = <&cpg 127>;

		};



		du: display@feb00000 {

			compatible = "renesas,du-r8a7742";

			reg = <0 0xfeb00000 0 0x70000>;