Commit a38a9949 authored by Marijn Suijten's avatar Marijn Suijten Committed by Dmitry Baryshkov
Browse files

drm/msm/dpu: Factor out shared interrupt register in INTF_BLK macro 



As the INTF block is going to attain more interrupts that don't share
the same MDP_SSPP_TOP0_INTR register, factor out the _reg argument for
the caller to construct the right interrupt index (register and bit
index) to not make the interrupt bit arguments depend on one of multiple
interrupt register indices.  This brings us more in line with how PP_BLK
specifies its interrupts and allows for better wrapping in the arrays.

Signed-off-by: default avatarMarijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/534222/
Link: https://lore.kernel.org/r/20230411-dpu-intf-te-v4-17-27ce1a5ab5c6@somainline.org


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent c31ec42e

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h

+12 −4
Original line number Diff line number Diff line
@@ -134,10 +134,18 @@ static const struct dpu_dspp_cfg msm8998_dspp[] = { 
};



static const struct dpu_intf_cfg msm8998_intf[] = {

	INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 21, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25),

	INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, 0, 21, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27),

	INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, 1, 21, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29),

	INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_HDMI, 0, 21, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31),

	INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 21, INTF_SDM845_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),

	INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, 0, 21, INTF_SDM845_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),

	INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, 1, 21, INTF_SDM845_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29)),

	INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_HDMI, 0, 21, INTF_SDM845_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),

};



static const struct dpu_perf_cfg msm8998_perf_data = {

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h

+12 −4
Original line number Diff line number Diff line
@@ -132,10 +132,18 @@ static const struct dpu_dsc_cfg sdm845_dsc[] = { 
};



static const struct dpu_intf_cfg sdm845_intf[] = {

	INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25),

	INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27),

	INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29),

	INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31),

	INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 24, INTF_SDM845_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),

	INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, 0, 24, INTF_SDM845_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),

	INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, 1, 24, INTF_SDM845_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29)),

	INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 1, 24, INTF_SDM845_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),

};



static const struct dpu_perf_cfg sdm845_perf_data = {

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h

+12 −4
Original line number Diff line number Diff line
@@ -162,10 +162,18 @@ static const struct dpu_dsc_cfg sm8150_dsc[] = { 
};



static const struct dpu_intf_cfg sm8150_intf[] = {

	INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),

	INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),

	INTF_BLK("intf_2", INTF_2, 0x6b000, 0x2bc, INTF_DSI, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29),

	INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31),

	INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 24, INTF_SC7180_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),

	INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, 0, 24, INTF_SC7180_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),

	INTF_BLK("intf_2", INTF_2, 0x6b000, 0x2bc, INTF_DSI, 1, 24, INTF_SC7180_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29)),

	INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 1, 24, INTF_SC7180_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),

};



static const struct dpu_perf_cfg sm8150_perf_data = {

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h

+18 −6
Original line number Diff line number Diff line
@@ -163,13 +163,25 @@ static const struct dpu_dsc_cfg sc8180x_dsc[] = { 
};



static const struct dpu_intf_cfg sc8180x_intf[] = {

	INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),

	INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),

	INTF_BLK("intf_2", INTF_2, 0x6b000, 0x2bc, INTF_DSI, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29),

	INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),

	INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, 0, 24, INTF_SC7180_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),

	INTF_BLK("intf_2", INTF_2, 0x6b000, 0x2bc, INTF_DSI, 1, 24, INTF_SC7180_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29)),

	/* INTF_3 is for MST, wired to INTF_DP 0 and 1, use dummy index until this is supported */

	INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 999, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31),

	INTF_BLK("intf_4", INTF_4, 0x6c000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 20, 21),

	INTF_BLK("intf_5", INTF_5, 0x6c800, 0x280, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 22, 23),

	INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 999, 24, INTF_SC7180_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),

	INTF_BLK("intf_4", INTF_4, 0x6c000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7180_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21)),

	INTF_BLK("intf_5", INTF_5, 0x6c800, 0x280, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7180_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23)),

};



static const struct dpu_perf_cfg sc8180x_perf_data = {

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h

+12 −4
Original line number Diff line number Diff line
@@ -163,10 +163,18 @@ static const struct dpu_dsc_cfg sm8250_dsc[] = { 
};



static const struct dpu_intf_cfg sm8250_intf[] = {

	INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),

	INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),

	INTF_BLK("intf_2", INTF_2, 0x6b000, 0x2c0, INTF_DSI, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29),

	INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31),

	INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 24, INTF_SC7180_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),

	INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),

	INTF_BLK("intf_2", INTF_2, 0x6b000, 0x2c0, INTF_DSI, 1, 24, INTF_SC7180_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29)),

	INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 1, 24, INTF_SC7180_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),

};



static const struct dpu_wb_cfg sm8250_wb[] = {