clk: renesas: r9a07g044: Add clock and reset entry for SCI1

Add clock and reset entry for SCI1 interface.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20211103160537.32253-1-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>