Commit 9fd4887c authored by Robert Foss's avatar Robert Foss Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: sm8350: Add DISPCC node 



Add the dispcc clock-controller DT node for sm8350.

Signed-off-by: default avatarRobert Foss <robert.foss@linaro.org>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220706154337.2026269-6-robert.foss@linaro.org
parent 1352b152

arch/arm64/boot/dts/qcom/sm8350.dtsi

+26 −0
Original line number Diff line number Diff line
@@ -4,6 +4,7 @@ 
 */



#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/clock/qcom,dispcc-sm8350.h>

#include <dt-bindings/clock/qcom,gcc-sm8350.h>

#include <dt-bindings/clock/qcom,rpmh.h>

#include <dt-bindings/dma/qcom-gpi.h>
@@ -2531,6 +2532,31 @@ usb_2_dwc3: usb@a800000 { 
			};

		};



		dispcc: clock-controller@af00000 {

			compatible = "qcom,sm8350-dispcc";

			reg = <0 0x0af00000 0 0x10000>;

			clocks = <&rpmhcc RPMH_CXO_CLK>,

				 <0>,

				 <0>,

				 <0>,

				 <0>,

				 <0>,

				 <0>;

			clock-names = "bi_tcxo",

				      "dsi0_phy_pll_out_byteclk",

				      "dsi0_phy_pll_out_dsiclk",

				      "dsi1_phy_pll_out_byteclk",

				      "dsi1_phy_pll_out_dsiclk",

				      "dp_phy_pll_link_clk",

				      "dp_phy_pll_vco_div_clk";

			#clock-cells = <1>;

			#reset-cells = <1>;

			#power-domain-cells = <1>;



			power-domains = <&rpmhpd SM8350_MMCX>;

			power-domain-names = "mmcx";

		};



		adsp: remoteproc@17300000 {

			compatible = "qcom,sm8350-adsp-pas";

			reg = <0 0x17300000 0 0x100>;