Commit 974e3bdc authored by Mauro Carvalho Chehab's avatar Mauro Carvalho Chehab Committed by Greg Kroah-Hartman
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staging: spmi: hisi-spmi-controller: adjust whitespaces at defines 



Some defines are not aligned with tab=8, which is the
style defined on Linux. Adjust them.

Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+huawei@kernel.org>
Link: https://lore.kernel.org/r/4a3799b40379dbc3abcbd08827977247ccc26dcb.1597647359.git.mchehab+huawei@kernel.org


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 6196331e

drivers/staging/hikey9xx/hisi-spmi-controller.c

+14 −12
Original line number Diff line number Diff line
@@ -42,14 +42,14 @@ 
#define SPMI_APB_SPMI_CMD_EN				BIT(31)

#define SPMI_APB_SPMI_CMD_TYPE_OFFSET			24

#define SPMI_APB_SPMI_CMD_LENGTH_OFFSET			20

#define SPMI_APB_SPMI_CMD_SLAVEID_OFFSET			16

#define SPMI_APB_SPMI_CMD_ADDR_OFFSET				0



#define bswap_32(X)   \

    ((((u32)(X) & 0xff000000) >> 24) | \

     (((u32)(X) & 0x00ff0000) >> 8) | \

     (((u32)(X) & 0x0000ff00) << 8) | \

     (((u32)(X) & 0x000000ff) << 24))

#define SPMI_APB_SPMI_CMD_SLAVEID_OFFSET		16

#define SPMI_APB_SPMI_CMD_ADDR_OFFSET			0



/* Command Opcodes */
@@ -78,7 +78,7 @@ enum spmi_controller_cmd_op_code { 


/* Maximum number of support PMIC peripherals */

#define SPMI_CONTROLLER_TIMEOUT_US		1000

#define SPMI_CONTROLLER_MAX_TRANS_BYTES	(16)

#define SPMI_CONTROLLER_MAX_TRANS_BYTES		16



/*

 * @base base address of the PMIC Arbiter core registers.
@@ -114,8 +114,10 @@ static int spmi_controller_wait_for_done(struct spmi_controller_dev *ctrl_dev, 
{

	u32 status = 0;

	u32 timeout = SPMI_CONTROLLER_TIMEOUT_US;

	u32 offset = SPMI_APB_SPMI_STATUS_BASE_ADDR + SPMI_CHANNEL_OFFSET * ctrl_dev->channel

		+ SPMI_SLAVE_OFFSET * sid;

	u32 offset;



	offset  = SPMI_APB_SPMI_STATUS_BASE_ADDR;

	offset += SPMI_CHANNEL_OFFSET * ctrl_dev->channel + SPMI_SLAVE_OFFSET * sid;



	while (timeout--) {

		status = readl(base + offset);