Commit 95870a88 authored by Rene Sapiens's avatar Rene Sapiens Committed by Greg Kroah-Hartman
Browse files

staging: ti dspbridge: Rename words with camel case. 



The intention of this patch is to rename the remaining variables with camel
case. Variables will be renamed avoiding camel case and Hungarian notation.
The words to be renamed in this patch are:
========================================
hStrm to stream_obj
iMode to io_mode
irqMask to irq_mask
lOffset to offset
memPtr to mem_ptr
moduleId to module_id
msgCallback to msg_callback
msgList to msg_list
nArgc to num_argc
nEntryStart to entry_start
nMemSpace to mem_space
nStatus to node_status
nStrms to strms
numLibs to num_libs
numLockedEntries to num_locked_entries
pageSize to page_sz
========================================

Signed-off-by: default avatarRene Sapiens <rene.sapiens@ti.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
parent e6890692

drivers/staging/tidspbridge/core/io_sm.c

+13 −13
Original line number Diff line number Diff line
@@ -133,16 +133,16 @@ struct io_mgr { 


/* Function Prototypes */

static void io_dispatch_chnl(IN struct io_mgr *pio_mgr,

				IN OUT struct chnl_object *pchnl, u8 iMode);

				IN OUT struct chnl_object *pchnl, u8 io_mode);

static void io_dispatch_msg(IN struct io_mgr *pio_mgr,

			    struct msg_mgr *hmsg_mgr);

static void io_dispatch_pm(struct io_mgr *pio_mgr);

static void notify_chnl_complete(struct chnl_object *pchnl,

				 struct chnl_irp *chnl_packet_obj);

static void input_chnl(struct io_mgr *pio_mgr, struct chnl_object *pchnl,

			u8 iMode);

			u8 io_mode);

static void output_chnl(struct io_mgr *pio_mgr, struct chnl_object *pchnl,

			u8 iMode);

			u8 io_mode);

static void input_msg(struct io_mgr *pio_mgr, struct msg_mgr *hmsg_mgr);

static void output_msg(struct io_mgr *pio_mgr, struct msg_mgr *hmsg_mgr);

static u32 find_ready_output(struct chnl_mgr *chnl_mgr_obj,
@@ -839,18 +839,18 @@ void io_cancel_chnl(struct io_mgr *hio_mgr, u32 ulChnl) 
 *      Proc-copy chanl dispatch.

 */

static void io_dispatch_chnl(IN struct io_mgr *pio_mgr,

				IN OUT struct chnl_object *pchnl, u8 iMode)

				IN OUT struct chnl_object *pchnl, u8 io_mode)

{

	if (!pio_mgr)

		goto func_end;



	/* See if there is any data available for transfer */

	if (iMode != IO_SERVICE)

	if (io_mode != IO_SERVICE)

		goto func_end;



	/* Any channel will do for this mode */

	input_chnl(pio_mgr, pchnl, iMode);

	output_chnl(pio_mgr, pchnl, iMode);

	input_chnl(pio_mgr, pchnl, io_mode);

	output_chnl(pio_mgr, pchnl, io_mode);

func_end:

	return;

}
@@ -1014,7 +1014,7 @@ void io_mbox_msg(u32 msg) 
 *      interrupts the DSP.

 */

void io_request_chnl(struct io_mgr *pio_mgr, struct chnl_object *pchnl,

			u8 iMode, OUT u16 *pwMbVal)

			u8 io_mode, OUT u16 *pwMbVal)

{

	struct chnl_mgr *chnl_mgr_obj;

	struct shm *sm;
@@ -1023,7 +1023,7 @@ void io_request_chnl(struct io_mgr *pio_mgr, struct chnl_object *pchnl, 
		goto func_end;

	chnl_mgr_obj = pio_mgr->hchnl_mgr;

	sm = pio_mgr->shared_mem;

	if (iMode == IO_INPUT) {

	if (io_mode == IO_INPUT) {

		/*

		 * Assertion fires if CHNL_AddIOReq() called on a stream

		 * which was cancelled, or attached to a dead board.
@@ -1034,7 +1034,7 @@ void io_request_chnl(struct io_mgr *pio_mgr, struct chnl_object *pchnl, 
		IO_OR_VALUE(pio_mgr->hbridge_context, struct shm, sm,

			    host_free_mask, (1 << pchnl->chnl_id));

		*pwMbVal = MBX_PCPY_CLASS;

	} else if (iMode == IO_OUTPUT) {

	} else if (io_mode == IO_OUTPUT) {

		/*

		 * This assertion fails if CHNL_AddIOReq() was called on a

		 * stream which was cancelled, or attached to a dead board.
@@ -1047,7 +1047,7 @@ void io_request_chnl(struct io_mgr *pio_mgr, struct chnl_object *pchnl, 
		 */

		chnl_mgr_obj->dw_output_mask |= (1 << pchnl->chnl_id);

	} else {

		DBC_ASSERT(iMode);	/* Shouldn't get here. */

		DBC_ASSERT(io_mode);	/* Shouldn't get here. */

	}

func_end:

	return;
@@ -1116,7 +1116,7 @@ static u32 find_ready_output(struct chnl_mgr *chnl_mgr_obj, 
 *      Dispatch a buffer on an input channel.

 */

static void input_chnl(struct io_mgr *pio_mgr, struct chnl_object *pchnl,

			u8 iMode)

			u8 io_mode)

{

	struct chnl_mgr *chnl_mgr_obj;

	struct shm *sm;
@@ -1403,7 +1403,7 @@ static void notify_chnl_complete(struct chnl_object *pchnl, 
 *      Dispatch a buffer on an output channel.

 */

static void output_chnl(struct io_mgr *pio_mgr, struct chnl_object *pchnl,

			u8 iMode)

			u8 io_mode)

{

	struct chnl_mgr *chnl_mgr_obj;

	struct shm *sm;

drivers/staging/tidspbridge/core/msg_sm.c

+12 −12
Original line number Diff line number Diff line
@@ -38,10 +38,10 @@ 
#include <dspbridge/dspmsg.h>



/*  ----------------------------------- Function Prototypes */

static int add_new_msg(struct lst_list *msgList);

static int add_new_msg(struct lst_list *msg_list);

static void delete_msg_mgr(struct msg_mgr *hmsg_mgr);

static void delete_msg_queue(struct msg_queue *msg_queue_obj, u32 uNumToDSP);

static void free_msg_list(struct lst_list *msgList);

static void free_msg_list(struct lst_list *msg_list);



/*

 *  ======== bridge_msg_create ========
@@ -50,13 +50,13 @@ static void free_msg_list(struct lst_list *msgList); 
 */

int bridge_msg_create(OUT struct msg_mgr **phMsgMgr,

			     struct dev_object *hdev_obj,

			     msg_onexit msgCallback)

			     msg_onexit msg_callback)

{

	struct msg_mgr *msg_mgr_obj;

	struct io_mgr *hio_mgr;

	int status = 0;



	if (!phMsgMgr || !msgCallback || !hdev_obj) {

	if (!phMsgMgr || !msg_callback || !hdev_obj) {

		status = -EFAULT;

		goto func_end;

	}
@@ -70,7 +70,7 @@ int bridge_msg_create(OUT struct msg_mgr **phMsgMgr, 
	msg_mgr_obj = kzalloc(sizeof(struct msg_mgr), GFP_KERNEL);



	if (msg_mgr_obj) {

		msg_mgr_obj->on_exit = msgCallback;

		msg_mgr_obj->on_exit = msg_callback;

		msg_mgr_obj->hio_mgr = hio_mgr;

		/* List of MSG_QUEUEs */

		msg_mgr_obj->queue_list = kzalloc(sizeof(struct lst_list),
@@ -551,7 +551,7 @@ void bridge_msg_set_queue_id(struct msg_queue *msg_queue_obj, u32 msgq_id) 
 *  ======== add_new_msg ========

 *      Must be called in message manager critical section.

 */

static int add_new_msg(struct lst_list *msgList)

static int add_new_msg(struct lst_list *msg_list)

{

	struct msg_frame *pmsg;

	int status = 0;
@@ -559,7 +559,7 @@ static int add_new_msg(struct lst_list *msgList) 
	pmsg = kzalloc(sizeof(struct msg_frame), GFP_ATOMIC);

	if (pmsg != NULL) {

		lst_init_elem((struct list_head *)pmsg);

		lst_put_tail(msgList, (struct list_head *)pmsg);

		lst_put_tail(msg_list, (struct list_head *)pmsg);

	} else {

		status = -ENOMEM;

	}
@@ -655,19 +655,19 @@ static void delete_msg_queue(struct msg_queue *msg_queue_obj, u32 uNumToDSP) 
/*

 *  ======== free_msg_list ========

 */

static void free_msg_list(struct lst_list *msgList)

static void free_msg_list(struct lst_list *msg_list)

{

	struct msg_frame *pmsg;



	if (!msgList)

	if (!msg_list)

		goto func_end;



	while ((pmsg = (struct msg_frame *)lst_get_head(msgList)) != NULL)

	while ((pmsg = (struct msg_frame *)lst_get_head(msg_list)) != NULL)

		kfree(pmsg);



	DBC_ASSERT(LST_IS_EMPTY(msgList));

	DBC_ASSERT(LST_IS_EMPTY(msg_list));



	kfree(msgList);

	kfree(msg_list);

func_end:

	return;

}

drivers/staging/tidspbridge/hw/hw_mmu.c

+21 −21
Original line number Diff line number Diff line
@@ -81,7 +81,7 @@ static hw_status mmu_flush_entry(const void __iomem *base_address); 
 *       TypE		: const u32

 *       Description     : Base Address of instance of MMU module

 *

 *       Identifier      : pageSize

 *       Identifier      : page_sz

 *       TypE		: const u32

 *       Description     : It indicates the page size

 *
@@ -113,7 +113,7 @@ static hw_status mmu_flush_entry(const void __iomem *base_address); 
 * METHOD:	       	: Check the Input parameters and set the CAM entry.

 */

static hw_status mmu_set_cam_entry(const void __iomem *base_address,

				   const u32 pageSize,

				   const u32 page_sz,

				   const u32 preservedBit,

				   const u32 validBit,

				   const u32 virtual_addr_tag);
@@ -184,11 +184,11 @@ hw_status hw_mmu_disable(const void __iomem *base_address) 
}



hw_status hw_mmu_num_locked_set(const void __iomem *base_address,

				u32 numLockedEntries)

				u32 num_locked_entries)

{

	hw_status status = RET_OK;



	MMUMMU_LOCK_BASE_VALUE_WRITE32(base_address, numLockedEntries);

	MMUMMU_LOCK_BASE_VALUE_WRITE32(base_address, num_locked_entries);



	return status;

}
@@ -203,44 +203,44 @@ hw_status hw_mmu_victim_num_set(const void __iomem *base_address, 
	return status;

}



hw_status hw_mmu_event_ack(const void __iomem *base_address, u32 irqMask)

hw_status hw_mmu_event_ack(const void __iomem *base_address, u32 irq_mask)

{

	hw_status status = RET_OK;



	MMUMMU_IRQSTATUS_WRITE_REGISTER32(base_address, irqMask);

	MMUMMU_IRQSTATUS_WRITE_REGISTER32(base_address, irq_mask);



	return status;

}



hw_status hw_mmu_event_disable(const void __iomem *base_address, u32 irqMask)

hw_status hw_mmu_event_disable(const void __iomem *base_address, u32 irq_mask)

{

	hw_status status = RET_OK;

	u32 irq_reg;



	irq_reg = MMUMMU_IRQENABLE_READ_REGISTER32(base_address);



	MMUMMU_IRQENABLE_WRITE_REGISTER32(base_address, irq_reg & ~irqMask);

	MMUMMU_IRQENABLE_WRITE_REGISTER32(base_address, irq_reg & ~irq_mask);



	return status;

}



hw_status hw_mmu_event_enable(const void __iomem *base_address, u32 irqMask)

hw_status hw_mmu_event_enable(const void __iomem *base_address, u32 irq_mask)

{

	hw_status status = RET_OK;

	u32 irq_reg;



	irq_reg = MMUMMU_IRQENABLE_READ_REGISTER32(base_address);



	MMUMMU_IRQENABLE_WRITE_REGISTER32(base_address, irq_reg | irqMask);

	MMUMMU_IRQENABLE_WRITE_REGISTER32(base_address, irq_reg | irq_mask);



	return status;

}



hw_status hw_mmu_event_status(const void __iomem *base_address, u32 *irqMask)

hw_status hw_mmu_event_status(const void __iomem *base_address, u32 *irq_mask)

{

	hw_status status = RET_OK;



	*irqMask = MMUMMU_IRQSTATUS_READ_REGISTER32(base_address);

	*irq_mask = MMUMMU_IRQSTATUS_READ_REGISTER32(base_address);



	return status;

}
@@ -294,13 +294,13 @@ hw_status hw_mmu_twl_disable(const void __iomem *base_address) 
}



hw_status hw_mmu_tlb_flush(const void __iomem *base_address, u32 virtualAddr,

			   u32 pageSize)

			   u32 page_sz)

{

	hw_status status = RET_OK;

	u32 virtual_addr_tag;

	enum hw_mmu_page_size_t pg_size_bits;



	switch (pageSize) {

	switch (page_sz) {

	case HW_PAGE_SIZE4KB:

		pg_size_bits = HW_MMU_SMALL_PAGE;

		break;
@@ -334,7 +334,7 @@ hw_status hw_mmu_tlb_flush(const void __iomem *base_address, u32 virtualAddr, 
hw_status hw_mmu_tlb_add(const void __iomem *base_address,

			 u32 physicalAddr,

			 u32 virtualAddr,

			 u32 pageSize,

			 u32 page_sz,

			 u32 entry_num,

			 struct hw_mmu_map_attrs_t *map_attrs,

			 s8 preservedBit, s8 validBit)
@@ -347,13 +347,13 @@ hw_status hw_mmu_tlb_add(const void __iomem *base_address, 
	/*Check the input Parameters */

	CHECK_INPUT_PARAM(base_address, 0, RET_BAD_NULL_PARAM,

			  RES_MMU_BASE + RES_INVALID_INPUT_PARAM);

	CHECK_INPUT_RANGE_MIN0(pageSize, MMU_PAGE_MAX, RET_PARAM_OUT_OF_RANGE,

	CHECK_INPUT_RANGE_MIN0(page_sz, MMU_PAGE_MAX, RET_PARAM_OUT_OF_RANGE,

			       RES_MMU_BASE + RES_INVALID_INPUT_PARAM);

	CHECK_INPUT_RANGE_MIN0(map_attrs->element_size, MMU_ELEMENTSIZE_MAX,

			       RET_PARAM_OUT_OF_RANGE, RES_MMU_BASE +

			       RES_INVALID_INPUT_PARAM);



	switch (pageSize) {

	switch (page_sz) {

	case HW_PAGE_SIZE4KB:

		mmu_pg_size = HW_MMU_SMALL_PAGE;

		break;
@@ -404,13 +404,13 @@ hw_status hw_mmu_tlb_add(const void __iomem *base_address, 
hw_status hw_mmu_pte_set(const u32 pg_tbl_va,

			 u32 physicalAddr,

			 u32 virtualAddr,

			 u32 pageSize, struct hw_mmu_map_attrs_t *map_attrs)

			 u32 page_sz, struct hw_mmu_map_attrs_t *map_attrs)

{

	hw_status status = RET_OK;

	u32 pte_addr, pte_val;

	s32 num_entries = 1;



	switch (pageSize) {

	switch (page_sz) {

	case HW_PAGE_SIZE4KB:

		pte_addr = hw_mmu_pte_addr_l2(pg_tbl_va,

					      virtualAddr &
@@ -537,7 +537,7 @@ static hw_status mmu_flush_entry(const void __iomem *base_address) 


/* mmu_set_cam_entry */

static hw_status mmu_set_cam_entry(const void __iomem *base_address,

				   const u32 pageSize,

				   const u32 page_sz,

				   const u32 preservedBit,

				   const u32 validBit,

				   const u32 virtual_addr_tag)
@@ -550,7 +550,7 @@ static hw_status mmu_set_cam_entry(const void __iomem *base_address, 
			  RES_MMU_BASE + RES_INVALID_INPUT_PARAM);



	mmu_cam_reg = (virtual_addr_tag << 12);

	mmu_cam_reg = (mmu_cam_reg) | (pageSize) | (validBit << 2) |

	mmu_cam_reg = (mmu_cam_reg) | (page_sz) | (validBit << 2) |

	    (preservedBit << 3);



	/* write values to register */

drivers/staging/tidspbridge/hw/hw_mmu.h

+8 −8
Original line number Diff line number Diff line
@@ -47,23 +47,23 @@ extern hw_status hw_mmu_enable(const void __iomem *base_address); 
extern hw_status hw_mmu_disable(const void __iomem *base_address);



extern hw_status hw_mmu_num_locked_set(const void __iomem *base_address,

				       u32 numLockedEntries);

				       u32 num_locked_entries);



extern hw_status hw_mmu_victim_num_set(const void __iomem *base_address,

				       u32 victimEntryNum);



/* For MMU faults */

extern hw_status hw_mmu_event_ack(const void __iomem *base_address,

				  u32 irqMask);

				  u32 irq_mask);



extern hw_status hw_mmu_event_disable(const void __iomem *base_address,

				      u32 irqMask);

				      u32 irq_mask);



extern hw_status hw_mmu_event_enable(const void __iomem *base_address,

				     u32 irqMask);

				     u32 irq_mask);



extern hw_status hw_mmu_event_status(const void __iomem *base_address,

				     u32 *irqMask);

				     u32 *irq_mask);



extern hw_status hw_mmu_fault_addr_read(const void __iomem *base_address,

					u32 *addr);
@@ -77,12 +77,12 @@ extern hw_status hw_mmu_twl_enable(const void __iomem *base_address); 
extern hw_status hw_mmu_twl_disable(const void __iomem *base_address);



extern hw_status hw_mmu_tlb_flush(const void __iomem *base_address,

				  u32 virtualAddr, u32 pageSize);

				  u32 virtualAddr, u32 page_sz);



extern hw_status hw_mmu_tlb_add(const void __iomem *base_address,

				u32 physicalAddr,

				u32 virtualAddr,

				u32 pageSize,

				u32 page_sz,

				u32 entry_num,

				struct hw_mmu_map_attrs_t *map_attrs,

				s8 preservedBit, s8 validBit);
@@ -91,7 +91,7 @@ extern hw_status hw_mmu_tlb_add(const void __iomem *base_address, 
extern hw_status hw_mmu_pte_set(const u32 pg_tbl_va,

				u32 physicalAddr,

				u32 virtualAddr,

				u32 pageSize,

				u32 page_sz,

				struct hw_mmu_map_attrs_t *map_attrs);



extern hw_status hw_mmu_pte_clear(const u32 pg_tbl_va,

drivers/staging/tidspbridge/include/dspbridge/cod.h

+4 −4
Original line number Diff line number Diff line
@@ -50,7 +50,7 @@ struct cod_attrs { 
 *  and freeing DSP memory.

 */

typedef u32(*cod_writefxn) (void *priv_ref, u32 ulDspAddr,

			    void *pbuf, u32 ul_num_bytes, u32 nMemSpace);

			    void *pbuf, u32 ul_num_bytes, u32 mem_space);



/*

 *  ======== cod_close ========
@@ -276,7 +276,7 @@ extern bool cod_init(void); 
 *      qualified pathname.

 *  Parameters:

 *      hmgr:       manager to load the code with

 *      nArgc:      number of arguments in the args array

 *      num_argc:   number of arguments in the args array

 *      args:       array of strings for arguments to DSP program

 *      write_fxn:   board-specific function to write data to DSP system

 *      pArb:       arbitrary pointer to be passed as first arg to write_fxn
@@ -287,14 +287,14 @@ extern bool cod_init(void); 
 *  Requires:

 *      COD module initialized.

 *      hmgr is valid.

 *      nArgc > 0.

 *      num_argc > 0.

 *      args != NULL.

 *      args[0] != NULL.

 *      pfn_write != NULL.

 *  Ensures:

 */

extern int cod_load_base(struct cod_manager *cod_mgr_obj,

				u32 nArgc, char *args[],

				u32 num_argc, char *args[],

				cod_writefxn pfn_write, void *pArb,

				char *envp[]);