Commit 948f0bf5 authored by Patrisious Haddad's avatar Patrisious Haddad Committed by Leon Romanovsky
Browse files

IB/mlx5: Add support for 800G_8X lane speed 



Add a check for 800G_8X speed when querying PTYS and report it back
correctly when needed.

Signed-off-by: default avatarPatrisious Haddad <phaddad@nvidia.com>
Reviewed-by: default avatarMark Zhang <markzhang@nvidia.com>
Link: https://lore.kernel.org/r/26fd0b6e1fac071c3eb779657bb3d8ba47f47c4f.1695204156.git.leon@kernel.org


Reviewed-by: default avatarJacob Keller <jacob.e.keller@intel.com>
Signed-off-by: default avatarLeon Romanovsky <leon@kernel.org>
parent 561b4a3a

drivers/infiniband/hw/mlx5/main.c

+4 −0
Original line number Diff line number Diff line
@@ -451,6 +451,10 @@ static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u16 *active_speed, 
		*active_width = IB_WIDTH_4X;

		*active_speed = IB_SPEED_NDR;

		break;

	case MLX5E_PROT_MASK(MLX5E_800GAUI_8_800GBASE_CR8_KR8):

		*active_width = IB_WIDTH_8X;

		*active_speed = IB_SPEED_NDR;

		break;

	default:

		return -EINVAL;

	}

drivers/net/ethernet/mellanox/mlx5/core/port.c

+1 −0
Original line number Diff line number Diff line
@@ -1102,6 +1102,7 @@ static const u32 mlx5e_ext_link_speed[MLX5E_EXT_LINK_MODES_NUMBER] = { 
	[MLX5E_100GAUI_1_100GBASE_CR_KR] = 100000,

	[MLX5E_200GAUI_2_200GBASE_CR2_KR2] = 200000,

	[MLX5E_400GAUI_4_400GBASE_CR4_KR4] = 400000,

	[MLX5E_800GAUI_8_800GBASE_CR8_KR8] = 800000,

};



int mlx5_port_query_eth_proto(struct mlx5_core_dev *dev, u8 port, bool ext,

include/linux/mlx5/port.h

+1 −0
Original line number Diff line number Diff line
@@ -117,6 +117,7 @@ enum mlx5e_ext_link_mode { 
	MLX5E_200GAUI_2_200GBASE_CR2_KR2	= 13,

	MLX5E_400GAUI_8				= 15,

	MLX5E_400GAUI_4_400GBASE_CR4_KR4	= 16,

	MLX5E_800GAUI_8_800GBASE_CR8_KR8	= 19,

	MLX5E_EXT_LINK_MODES_NUMBER,

};