Commit 914b8de3 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'tegra-for-5.11-arm64-dt' of... 

Merge tag 'tegra-for-5.11-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt

arm64: tegra: Device tree changes for v5.11-rc1

These changes are mostly minor fixes across the board, but they also
enable PMUs on Tegra186 and enable SATA support on Jetson TX2.

* tag 'tegra-for-5.11-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  arm64: tegra: Fix Tegra194 HDA {clock,reset}-names ordering
  arm64: tegra: Enable AHCI on Jetson TX2
  arm64: tegra: Change order of SATA resets for Tegra132 and Tegra210
  arm64: tegra: Add XUSB pad controller interrupt
  arm64: tegra: Rename ADMA device nodes for Tegra210
  arm64: tegra: Hook up edp interrupt on Tegra132 SOCTHERM
  arm64: tegra: Add missing hot temperatures to Tegra210 thermal-zones
  arm64: tegra: Add missing gpu-throt-level to Tegra210 soctherm
  arm64: tegra: Add missing hot temperatures to Tegra132 thermal-zones
  arm64: tegra: Fix DT binding for IO High Voltage entry
  arm64: tegra: Fix GIC400 missing GICH/GICV register regions
  arm64: tegra: Add missing CPU PMUs on Tegra186
  arm64: tegra: Fix Tegra234 VDK node names
  arm64: tegra: Wrong AON HSP reg property size
  arm64: tegra: Fix USB_VBUS_EN0 regulator on Jetson TX1
  arm64: tegra: Correct the UART for Jetson Xavier NX
  arm64: tegra: Disable the ACONNECT for Jetson TX2

Link: https://lore.kernel.org/r/20201127144329.124891-5-thierry.reding@gmail.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 9c49a39c 48f6e195

arch/arm64/boot/dts/nvidia/tegra132.dtsi

+16 −4
Original line number Diff line number Diff line
@@ -629,9 +629,9 @@ sata@70020000 { 
			 <&tegra_car TEGRA124_CLK_PLL_E>;

		clock-names = "sata", "sata-oob", "cml1", "pll_e";

		resets = <&tegra_car 124>,

			 <&tegra_car 123>,

			 <&tegra_car 129>;

		reset-names = "sata", "sata-oob", "sata-cold";

			 <&tegra_car 129>,

			 <&tegra_car 123>;

		reset-names = "sata", "sata-cold", "sata-oob";

		status = "disabled";

	};
@@ -865,7 +865,9 @@ soctherm: thermal-sensor@700e2000 { 
		reg = <0x0 0x700e2000 0x0 0x600>, /* 0: SOC_THERM reg_base */

		      <0x0 0x70040000 0x0 0x200>; /* 2: CCROC reg_base */

		reg-names = "soctherm-reg", "ccroc-reg";

		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;

		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "thermal", "edp";

		clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,

		         <&tegra_car TEGRA124_CLK_SOC_THERM>;

		clock-names = "tsensor", "soctherm";
@@ -925,6 +927,11 @@ mem_shutdown_trip { 
					hysteresis = <1000>;

					type = "critical";

				};

				mem_throttle_trip {

					temperature = <99000>;

					hysteresis = <1000>;

					type = "hot";

				};

			};



			cooling-maps {
@@ -975,6 +982,11 @@ pllx_shutdown_trip { 
					hysteresis = <1000>;

					type = "critical";

				};

				pllx_throttle_trip {

					temperature = <99000>;

					hysteresis = <1000>;

					type = "hot";

				};

			};



			cooling-maps {

arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts

+4 −12
Original line number Diff line number Diff line
@@ -10,18 +10,6 @@ / { 
	model = "NVIDIA Jetson TX2 Developer Kit";

	compatible = "nvidia,p2771-0000", "nvidia,tegra186";



	aconnect {

		status = "okay";



		dma-controller@2930000 {

			status = "okay";

		};



		interrupt-controller@2a40000 {

			status = "okay";

		};

	};



	i2c@3160000 {

		power-monitor@42 {

			compatible = "ti,ina3221";
@@ -297,6 +285,10 @@ dpaux@155c0000 { 
		};

	};



	sata@3507000 {

		status = "okay";

	};



	gpio-keys {

		compatible = "gpio-keys";

arch/arm64/boot/dts/nvidia/tegra186.dtsi

+54 −7
Original line number Diff line number Diff line
@@ -685,6 +685,7 @@ padctl: padctl@3520000 { 
		reg = <0x0 0x03520000 0x0 0x1000>,

		      <0x0 0x03540000 0x0 0x1000>;

		reg-names = "padctl", "ao";

		interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;



		resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>;

		reset-names = "padctl";
@@ -845,7 +846,9 @@ gic: interrupt-controller@3881000 { 
		#interrupt-cells = <3>;

		interrupt-controller;

		reg = <0x0 0x03881000 0x0 0x1000>,

		      <0x0 0x03882000 0x0 0x2000>;

		      <0x0 0x03882000 0x0 0x2000>,

		      <0x0 0x03884000 0x0 0x2000>,

		      <0x0 0x03886000 0x0 0x2000>;

		interrupts = <GIC_PPI 9

			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;

		interrupt-parent = <&gic>;
@@ -1501,6 +1504,34 @@ cpu_bpmp_rx: sram@4f000 { 
		};

	};



	sata@3507000 {

		compatible = "nvidia,tegra186-ahci";

		reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */

		      <0x0 0x03500000 0x0 0x00007000>, /* SATA */

		      <0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */

		interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;



		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>;

		interconnects = <&mc TEGRA186_MEMORY_CLIENT_SATAR &emc>,

				<&mc TEGRA186_MEMORY_CLIENT_SATAW &emc>;

		interconnect-names = "dma-mem", "write";

		iommus = <&smmu TEGRA186_SID_SATA>;



		clocks = <&bpmp TEGRA186_CLK_SATA>,

			 <&bpmp TEGRA186_CLK_SATA_OOB>;

		clock-names = "sata", "sata-oob";

		assigned-clocks = <&bpmp TEGRA186_CLK_SATA>,

				  <&bpmp TEGRA186_CLK_SATA_OOB>;

		assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>,

					 <&bpmp TEGRA186_CLK_PLLP>;

		assigned-clock-rates = <102000000>,

				       <204000000>;

		resets = <&bpmp TEGRA186_RESET_SATA>,

			<&bpmp TEGRA186_RESET_SATACOLD>;

		reset-names = "sata", "sata-cold";

		status = "disabled";

	};



	bpmp: bpmp {

		compatible = "nvidia,tegra186-bpmp";

		interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>,
@@ -1534,7 +1565,7 @@ cpus { 
		#address-cells = <1>;

		#size-cells = <0>;



		cpu@0 {

		denver_0: cpu@0 {

			compatible = "nvidia,tegra186-denver";

			device_type = "cpu";

			i-cache-size = <0x20000>;
@@ -1547,7 +1578,7 @@ cpu@0 { 
			reg = <0x000>;

		};



		cpu@1 {

		denver_1: cpu@1 {

			compatible = "nvidia,tegra186-denver";

			device_type = "cpu";

			i-cache-size = <0x20000>;
@@ -1560,7 +1591,7 @@ cpu@1 { 
			reg = <0x001>;

		};



		cpu@2 {

		ca57_0: cpu@2 {

			compatible = "arm,cortex-a57";

			device_type = "cpu";

			i-cache-size = <0xC000>;
@@ -1573,7 +1604,7 @@ cpu@2 { 
			reg = <0x100>;

		};



		cpu@3 {

		ca57_1: cpu@3 {

			compatible = "arm,cortex-a57";

			device_type = "cpu";

			i-cache-size = <0xC000>;
@@ -1586,7 +1617,7 @@ cpu@3 { 
			reg = <0x101>;

		};



		cpu@4 {

		ca57_2: cpu@4 {

			compatible = "arm,cortex-a57";

			device_type = "cpu";

			i-cache-size = <0xC000>;
@@ -1599,7 +1630,7 @@ cpu@4 { 
			reg = <0x102>;

		};



		cpu@5 {

		ca57_3: cpu@5 {

			compatible = "arm,cortex-a57";

			device_type = "cpu";

			i-cache-size = <0xC000>;
@@ -1631,6 +1662,22 @@ L2_A57: l2-cache1 { 
		};

	};



	pmu_denver {

		compatible = "nvidia,denver-pmu", "arm,armv8-pmuv3";

		interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-affinity = <&denver_0 &denver_1>;

	};



	pmu_a57 {

		compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3";

		interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>;

	};



	thermal-zones {

		a57 {

			polling-delay = <0>;

arch/arm64/boot/dts/nvidia/tegra194-p3668-0000.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -54,7 +54,7 @@ memory-controller@2c00000 { 
			status = "okay";

		};



		serial@c280000 {

		serial@3100000 {

			status = "okay";

		};

arch/arm64/boot/dts/nvidia/tegra194.dtsi

+10 −9
Original line number Diff line number Diff line
@@ -378,7 +378,7 @@ pex_rst { 
					nvidia,schmitt = <TEGRA_PIN_DISABLE>;

					nvidia,lpdr = <TEGRA_PIN_ENABLE>;

					nvidia,enable-input = <TEGRA_PIN_DISABLE>;

					nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;

					nvidia,io-hv = <TEGRA_PIN_ENABLE>;

					nvidia,tristate = <TEGRA_PIN_DISABLE>;

					nvidia,pull = <TEGRA_PIN_PULL_NONE>;

				};
@@ -390,7 +390,7 @@ clkreq { 
					nvidia,schmitt = <TEGRA_PIN_DISABLE>;

					nvidia,lpdr = <TEGRA_PIN_ENABLE>;

					nvidia,enable-input = <TEGRA_PIN_ENABLE>;

					nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;

					nvidia,io-hv = <TEGRA_PIN_ENABLE>;

					nvidia,tristate = <TEGRA_PIN_DISABLE>;

					nvidia,pull = <TEGRA_PIN_PULL_NONE>;

				};
@@ -782,13 +782,13 @@ hda@3510000 { 
			reg = <0x3510000 0x10000>;

			interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&bpmp TEGRA194_CLK_HDA>,

				 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>,

				 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>;

			clock-names = "hda", "hda2codec_2x", "hda2hdmi";

				 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>,

				 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>;

			clock-names = "hda", "hda2hdmi", "hda2codec_2x";

			resets = <&bpmp TEGRA194_RESET_HDA>,

				 <&bpmp TEGRA194_RESET_HDA2CODEC_2X>,

				 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>;

			reset-names = "hda", "hda2codec_2x", "hda2hdmi";

				 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>,

				 <&bpmp TEGRA194_RESET_HDA2CODEC_2X>;

			reset-names = "hda", "hda2hdmi", "hda2codec_2x";

			power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;

			interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>,

					<&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>;
@@ -801,6 +801,7 @@ xusb_padctl: padctl@3520000 { 
			reg = <0x03520000 0x1000>,

			      <0x03540000 0x1000>;

			reg-names = "padctl", "ao";

			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;



			resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>;

			reset-names = "padctl";
@@ -1161,7 +1162,7 @@ p2u_hsio_11: phy@3f40000 { 


		hsp_aon: hsp@c150000 {

			compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp";

			reg = <0x0c150000 0xa0000>;

			reg = <0x0c150000 0x90000>;

			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,

			             <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,

			             <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,