Commit 8bdd369d authored by Geert Uytterhoeven's avatar Geert Uytterhoeven
Browse files

pinctrl: renesas: r8a779f0: Fix GPIO function on I2C-capable pins 



Unlike on R-Car Gen3 SoCs, setting a bit to zero in a GPIO / Peripheral
Function Select Register (GPSRn) on R-Car S4-8 is not always sufficient
to configure a pin for GPIO.  For I2C-capable pins, the I2C function
must also be explicitly disabled in the corresponding Module Select
Register (MODSELn).

Add the missing FN_SEL_I2Ci_0 function enums to the pinmux_data[] array
by temporarily overriding the GP_1_j_FN function enum to expand to two
enums: the original GP_1_j_FN enum to configure the GPSR register bits,
and the missing FN_SEL_I2Ci_0 enum to configure the MODSEL register
bits.

Fixes: 030ac6d7 ("pinctrl: renesas: Initial R8A779F0 PFC support")
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/c12c60ec1058140a37f03650043ab73f730f104f.1650610471.git.geert+renesas@glider.be
parent 4288caed

drivers/pinctrl/renesas/pfc-r8a779f0.c

+21 −0
Original line number Diff line number Diff line
@@ -257,7 +257,28 @@ enum { 
};



static const u16 pinmux_data[] = {

/* Using GP_1_[0-9] requires disabling I2C in MOD_SEL1 */

#define GP_1_0_FN	GP_1_0_FN,	FN_SEL_I2C0_0

#define GP_1_1_FN	GP_1_1_FN,	FN_SEL_I2C0_0

#define GP_1_2_FN	GP_1_2_FN,	FN_SEL_I2C1_0

#define GP_1_3_FN	GP_1_3_FN,	FN_SEL_I2C1_0

#define GP_1_4_FN	GP_1_4_FN,	FN_SEL_I2C2_0

#define GP_1_5_FN	GP_1_5_FN,	FN_SEL_I2C2_0

#define GP_1_6_FN	GP_1_6_FN,	FN_SEL_I2C3_0

#define GP_1_7_FN	GP_1_7_FN,	FN_SEL_I2C3_0

#define GP_1_8_FN	GP_1_8_FN,	FN_SEL_I2C4_0

#define GP_1_9_FN	GP_1_9_FN,	FN_SEL_I2C4_0

	PINMUX_DATA_GP_ALL(),

#undef GP_1_0_FN

#undef GP_1_1_FN

#undef GP_1_2_FN

#undef GP_1_3_FN

#undef GP_1_4_FN

#undef GP_1_5_FN

#undef GP_1_6_FN

#undef GP_1_7_FN

#undef GP_1_8_FN

#undef GP_1_9_FN



	PINMUX_SINGLE(SD_WP),

	PINMUX_SINGLE(SD_CD),