Commit 86b812dc authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/controller/aspm' 

- Add a dwc .host_post_init() callback for configuration after downstream
  devices are scanned (Manivannan Sadhasivam)

- Enable ASPM for devices below qcom 1.9.0 host controllers (Manivannan
  Sadhasivam)

* pci/controller/aspm:
  PCI: qcom: Enable ASPM for platforms supporting 1.9.0 ops
  PCI: dwc: Add host_post_init() callback
parents dbf9527c 9f4f3dfa

drivers/pci/controller/dwc/pcie-designware-host.c

+3 −0
Original line number Diff line number Diff line
@@ -502,6 +502,9 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) 
	if (ret)

		goto err_stop_link;



	if (pp->ops->host_post_init)

		pp->ops->host_post_init(pp);



	return 0;



err_stop_link:

drivers/pci/controller/dwc/pcie-designware.h

+1 −0
Original line number Diff line number Diff line
@@ -301,6 +301,7 @@ enum dw_pcie_ltssm { 
struct dw_pcie_host_ops {

	int (*host_init)(struct dw_pcie_rp *pp);

	void (*host_deinit)(struct dw_pcie_rp *pp);

	void (*host_post_init)(struct dw_pcie_rp *pp);

	int (*msi_host_init)(struct dw_pcie_rp *pp);

	void (*pme_turn_off)(struct dw_pcie_rp *pp);

};

drivers/pci/controller/dwc/pcie-qcom.c

+28 −0
Original line number Diff line number Diff line
@@ -219,6 +219,7 @@ struct qcom_pcie_ops { 
	int (*get_resources)(struct qcom_pcie *pcie);

	int (*init)(struct qcom_pcie *pcie);

	int (*post_init)(struct qcom_pcie *pcie);

	void (*host_post_init)(struct qcom_pcie *pcie);

	void (*deinit)(struct qcom_pcie *pcie);

	void (*ltssm_enable)(struct qcom_pcie *pcie);

	int (*config_sid)(struct qcom_pcie *pcie);
@@ -964,6 +965,22 @@ static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie) 
	return 0;

}



static int qcom_pcie_enable_aspm(struct pci_dev *pdev, void *userdata)

{

	/* Downstream devices need to be in D0 state before enabling PCI PM substates */

	pci_set_power_state(pdev, PCI_D0);

	pci_enable_link_state(pdev, PCIE_LINK_STATE_ALL);



	return 0;

}



static void qcom_pcie_host_post_init_2_7_0(struct qcom_pcie *pcie)

{

	struct dw_pcie_rp *pp = &pcie->pci->pp;



	pci_walk_bus(pp->bridge->bus, qcom_pcie_enable_aspm, NULL);

}



static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie)

{

	struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
@@ -1216,9 +1233,19 @@ static void qcom_pcie_host_deinit(struct dw_pcie_rp *pp) 
	pcie->cfg->ops->deinit(pcie);

}



static void qcom_pcie_host_post_init(struct dw_pcie_rp *pp)

{

	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);

	struct qcom_pcie *pcie = to_qcom_pcie(pci);



	if (pcie->cfg->ops->host_post_init)

		pcie->cfg->ops->host_post_init(pcie);

}



static const struct dw_pcie_host_ops qcom_pcie_dw_ops = {

	.host_init	= qcom_pcie_host_init,

	.host_deinit	= qcom_pcie_host_deinit,

	.host_post_init	= qcom_pcie_host_post_init,

};



/* Qcom IP rev.: 2.1.0	Synopsys IP rev.: 4.01a */
@@ -1280,6 +1307,7 @@ static const struct qcom_pcie_ops ops_1_9_0 = { 
	.get_resources = qcom_pcie_get_resources_2_7_0,

	.init = qcom_pcie_init_2_7_0,

	.post_init = qcom_pcie_post_init_2_7_0,

	.host_post_init = qcom_pcie_host_post_init_2_7_0,

	.deinit = qcom_pcie_deinit_2_7_0,

	.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,

	.config_sid = qcom_pcie_config_sid_1_9_0,