Commit 864fdbe7 authored by Gerald Baeza's avatar Gerald Baeza Committed by Alexandre Torgue
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ARM: dts: stm32: update sdmmc slew-rate in stm32mp13 pinctrl 



SDMMC1/2 CK <= 50 MHz so slew-rate = <1>
A new node sdmmc1-clk-0 is added to manage the new clock pin slew-rate.

Signed-off-by: default avatarGerald Baeza <gerald.baeza@foss.st.com>
Signed-off-by: default avatarYann Gautier <yann.gautier@foss.st.com>
Signed-off-by: default avatarAlexandre Torgue <alexandre.torgue@foss.st.com>
parent 2434845b

arch/arm/boot/dts/stm32mp13-pinctrl.dtsi

+10 −13
Original line number Diff line number Diff line
@@ -7,7 +7,7 @@ 


&pinctrl {

	sdmmc1_b4_pins_a: sdmmc1-b4-0 {

		pins1 {

		pins {

			pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */

				 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */

				 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
@@ -17,12 +17,6 @@ pins1 { 
			drive-push-pull;

			bias-disable;

		};

		pins2 {

			pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */

			slew-rate = <2>;

			drive-push-pull;

			bias-disable;

		};

	};



	sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
@@ -36,12 +30,6 @@ pins1 { 
			bias-disable;

		};

		pins2 {

			pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */

			slew-rate = <2>;

			drive-push-pull;

			bias-disable;

		};

		pins3 {

			pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */

			slew-rate = <1>;

			drive-open-drain;
@@ -49,6 +37,15 @@ pins3 { 
		};

	};



	sdmmc1_clk_pins_a: sdmmc1-clk-0 {

		pins {

			pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */

			slew-rate = <1>;

			drive-push-pull;

			bias-disable;

		};

	};



	uart4_pins_a: uart4-0 {

		pins1 {

			pinmux = <STM32_PINMUX('D', 6, AF8)>; /* UART4_TX */