Commit 8534575f authored by Eric Bernstein's avatar Eric Bernstein Committed by Alex Deucher
Browse files

drm/amd/display: Expose some MPC functions for reuse 



Signed-off-by: default avatarEric Bernstein <eric.bernstein@amd.com>
Reviewed-by: default avatarEric Bernstein <Eric.Bernstein@amd.com>
Acked-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 80e80ec8

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c

+5 −6
Original line number Diff line number Diff line
@@ -65,7 +65,7 @@ static void mpc10_set_bg_color( 
			MPCC_BG_B_CB, bg_b_cb);

}



static void mpc10_assert_idle_mpcc(struct mpc *mpc, int id)

void mpc10_assert_idle_mpcc(struct mpc *mpc, int id)

{

	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
@@ -116,7 +116,7 @@ static void mpc10_assert_mpcc_idle_before_connect(struct dcn10_mpc *mpc10, int i 
	}

}



static void mpc10_mpcc_remove(

void mpc10_mpcc_remove(

		struct mpc *mpc,

		struct mpc_tree_cfg *tree_cfg,

		int opp_id,
@@ -265,7 +265,7 @@ static void mpc10_add_to_tree_cfg( 
	tree_cfg->num_pipes++;

}



static int mpc10_mpcc_add(struct mpc *mpc, struct mpcc_cfg *cfg)

int mpc10_mpcc_add(struct mpc *mpc, struct mpcc_cfg *cfg)

{

	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);

	int mpcc_id, z_idx;
@@ -313,7 +313,7 @@ static int mpc10_mpcc_add(struct mpc *mpc, struct mpcc_cfg *cfg) 
	return mpcc_id;

}



static void mpc10_update_blend_mode(

void mpc10_update_blend_mode(

		struct mpc *mpc,

		struct mpcc_cfg *cfg)

{
@@ -339,8 +339,7 @@ const struct mpc_funcs dcn10_mpc_funcs = { 
		.add = mpc10_mpcc_add,

		.remove = mpc10_mpcc_remove,

		.wait_for_idle = mpc10_assert_idle_mpcc,

		.set_denorm = NULL,

		.update_blend_mode = mpc10_update_blend_mode

		.update_blend_mode = mpc10_update_blend_mode,

};



void dcn10_mpc_construct(struct dcn10_mpc *mpc10,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h

+34 −11
Original line number Diff line number Diff line
@@ -34,7 +34,6 @@ 
#define MAX_OPP 6



#define MPC_COMMON_REG_LIST_DCN1_0(inst) \

	SRII(MUX, MPC_OUT, inst),\

	SRII(MPCC_TOP_SEL, MPCC, inst),\

	SRII(MPCC_BOT_SEL, MPCC, inst),\

	SRII(MPCC_CONTROL, MPCC, inst),\
@@ -45,17 +44,19 @@ 
	SRII(MPCC_BG_B_CB, MPCC, inst),\

	SRII(MPCC_BG_B_CB, MPCC, inst)



struct dcn_mpc_registers {

	uint32_t MPCC_TOP_SEL[MAX_MPCC];

	uint32_t MPCC_BOT_SEL[MAX_MPCC];

	uint32_t MPCC_CONTROL[MAX_MPCC];

	uint32_t MPCC_STATUS[MAX_MPCC];

	uint32_t MPCC_OPP_ID[MAX_MPCC];

	uint32_t MPCC_BG_G_Y[MAX_MPCC];

	uint32_t MPCC_BG_R_CR[MAX_MPCC];

	uint32_t MPCC_BG_B_CB[MAX_MPCC];

#define MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(inst) \

	SRII(MUX, MPC_OUT, inst)



#define MPC_COMMON_REG_VARIABLE_LIST \

	uint32_t MPCC_TOP_SEL[MAX_MPCC]; \

	uint32_t MPCC_BOT_SEL[MAX_MPCC]; \

	uint32_t MPCC_CONTROL[MAX_MPCC]; \

	uint32_t MPCC_STATUS[MAX_MPCC]; \

	uint32_t MPCC_OPP_ID[MAX_MPCC]; \

	uint32_t MPCC_BG_G_Y[MAX_MPCC]; \

	uint32_t MPCC_BG_R_CR[MAX_MPCC]; \

	uint32_t MPCC_BG_B_CB[MAX_MPCC]; \

	uint32_t MUX[MAX_OPP];

};



#define MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\

	SF(MPCC0_MPCC_TOP_SEL, MPCC_TOP_SEL, mask_sh),\
@@ -87,6 +88,10 @@ struct dcn_mpc_registers { 
	type MPCC_BG_B_CB;\

	type MPC_OUT_MUX;



struct dcn_mpc_registers {

	MPC_COMMON_REG_VARIABLE_LIST

};



struct dcn_mpc_shift {

	MPC_REG_FIELD_LIST(uint8_t)

};
@@ -112,4 +117,22 @@ void dcn10_mpc_construct(struct dcn10_mpc *mpcc10, 
	const struct dcn_mpc_mask *mpc_mask,

	int num_mpcc);



int mpc10_mpcc_add(

		struct mpc *mpc,

		struct mpcc_cfg *cfg);



void mpc10_mpcc_remove(

		struct mpc *mpc,

		struct mpc_tree_cfg *tree_cfg,

		int opp_id,

		int dpp_id);



void mpc10_assert_idle_mpcc(

		struct mpc *mpc,

		int id);



void mpc10_update_blend_mode(

		struct mpc *mpc,

		struct mpcc_cfg *cfg);



#endif

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c

+5 −1
Original line number Diff line number Diff line
@@ -329,7 +329,11 @@ static const struct dcn_mpc_registers mpc_regs = { 
		MPC_COMMON_REG_LIST_DCN1_0(0),

		MPC_COMMON_REG_LIST_DCN1_0(1),

		MPC_COMMON_REG_LIST_DCN1_0(2),

		MPC_COMMON_REG_LIST_DCN1_0(3)

		MPC_COMMON_REG_LIST_DCN1_0(3),

		MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(0),

		MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(1),

		MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(2),

		MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(3)

};



static const struct dcn_mpc_shift mpc_shift = {

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

+4 −3
Original line number Diff line number Diff line
@@ -46,15 +46,16 @@ struct mpc { 


struct mpc_funcs {

	int (*add)(struct mpc *mpc, struct mpcc_cfg *cfg);



	void (*remove)(struct mpc *mpc,

			struct mpc_tree_cfg *tree_cfg,

			int opp_id,

			int mpcc_inst);



	void (*wait_for_idle)(struct mpc *mpc, int id);

	void (*set_denorm)(struct mpc *mpc,

			int opp_id,

			enum dc_color_depth output_depth);



	void (*update_blend_mode)(struct mpc *mpc, struct mpcc_cfg *cfg);



};



#endif