Commit 82f4ab32 authored by Charlene Liu's avatar Charlene Liu Committed by Alex Deucher
Browse files

drm/amd/display: Add z8_marks related in dml for DCN35 



Add z8 watermarks to struct for DCN35.

Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: default avatarAlvin Lee <alvin.lee2@amd.com>
Acked-by: default avatarQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: default avatarCharlene Liu <charlene.liu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f1eb0456

drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hubbub.c

+34 −0
Original line number Diff line number Diff line
@@ -379,6 +379,17 @@ static void hubbub35_init_watermarks(struct hubbub *hubbub) 
	REG_WRITE(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, reg);

	REG_WRITE(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C, reg);

	REG_WRITE(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D, reg);



	reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A);

	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B, reg);

	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C, reg);

	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D, reg);



	reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A);

	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, reg);

	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, reg);

	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, reg);



}



static void hubbub35_wm_read_state(struct hubbub *hubbub,
@@ -409,6 +420,11 @@ static void hubbub35_wm_read_state(struct hubbub *hubbub, 
	REG_GET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A,

			 DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A, &s->fclk_pstate_change);



	REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A,

			DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A, &s->sr_enter_exit_Z8);



	REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A,

			DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A, &s->sr_enter_Z8);

	s = &wm->sets[1];

	s->wm_set = 1;

	REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B,
@@ -429,6 +445,12 @@ static void hubbub35_wm_read_state(struct hubbub *hubbub, 
	REG_GET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B,

			DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, &s->fclk_pstate_change);



	REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B,

			DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, &s->sr_enter_exit_Z8);



	REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B,

			DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B, &s->sr_enter_Z8);



	s = &wm->sets[2];

	s->wm_set = 2;

	REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C,
@@ -449,6 +471,12 @@ static void hubbub35_wm_read_state(struct hubbub *hubbub, 
	REG_GET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C,

			DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C, &s->fclk_pstate_change);



	REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C,

			DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, &s->sr_enter_exit_Z8);



	REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C,

			DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C, &s->sr_enter_Z8);



	s = &wm->sets[3];

	s->wm_set = 3;

	REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D,
@@ -468,6 +496,12 @@ static void hubbub35_wm_read_state(struct hubbub *hubbub, 


	REG_GET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D,

			DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D, &s->fclk_pstate_change);



	REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D,

			DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, &s->sr_enter_exit_Z8);



	REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D,

			DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D, &s->sr_enter_Z8);

}



static void hubbub35_set_fgcg(struct dcn20_hubbub *hubbub2, bool enable)

drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c

+2 −1
Original line number Diff line number Diff line
@@ -1677,6 +1677,7 @@ static bool dcn35_validate_bandwidth(struct dc *dc, 
	return out;

}





static struct resource_funcs dcn35_res_pool_funcs = {

	.destroy = dcn35_destroy_resource_pool,

	.link_enc_create = dcn35_link_encoder_create,
@@ -1685,7 +1686,7 @@ static struct resource_funcs dcn35_res_pool_funcs = { 
	.link_enc_unassign = link_enc_cfg_link_enc_unassign,

	.panel_cntl_create = dcn31_panel_cntl_create,

	.validate_bandwidth = dcn35_validate_bandwidth,

	.calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg,

	.calculate_wm_and_dlg = NULL,

	.update_soc_for_wm_a = dcn31_update_soc_for_wm_a,

	.populate_dml_pipes = dcn35_populate_dml_pipes_from_context_fpu,

	.acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,