Commit 8148dfba authored by Hannes Reinecke's avatar Hannes Reinecke Committed by Martin K. Petersen
Browse files

scsi: 3w-xxxx: Whitespace cleanup 

Link: https://lore.kernel.org/r/20210113090500.129644-3-hare@suse.de


Signed-off-by: default avatarHannes Reinecke <hare@suse.de>
Signed-off-by: default avatarMartin K. Petersen <martin.petersen@oracle.com>
parent 0653c358

drivers/scsi/3w-xxxx.c

+125 −126
Original line number Diff line number Diff line
@@ -1979,7 +1979,6 @@ static int tw_scsi_queue_lck(struct scsi_cmnd *SCpnt, void (*done)(struct scsi_c 
		printk(KERN_NOTICE "3w-xxxx: scsi%d: Unknown scsi opcode: 0x%x\n", tw_dev->host->host_no, *command);

		tw_dev->state[request_id] = TW_S_COMPLETED;

		tw_state_request_finish(tw_dev, request_id);

			SCpnt->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION;

		scsi_build_sense_buffer(1, SCpnt->sense_buffer, ILLEGAL_REQUEST, 0x20, 0);

		done(SCpnt);

		retval = 0;

drivers/scsi/3w-xxxx.h

+104 −95
Original line number Diff line number Diff line
@@ -250,13 +250,22 @@ static unsigned char tw_sense_table[][4] = 
#define TW_STATUS_REG_ADDR(x) (x->base_addr + 0x4)

#define TW_COMMAND_QUEUE_REG_ADDR(x) (x->base_addr + 0x8)

#define TW_RESPONSE_QUEUE_REG_ADDR(x) (x->base_addr + 0xC)

#define TW_CLEAR_ALL_INTERRUPTS(x) (outl(TW_STATUS_VALID_INTERRUPT, TW_CONTROL_REG_ADDR(x)))

#define TW_CLEAR_ATTENTION_INTERRUPT(x) (outl(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT, TW_CONTROL_REG_ADDR(x)))

#define TW_CLEAR_HOST_INTERRUPT(x) (outl(TW_CONTROL_CLEAR_HOST_INTERRUPT, TW_CONTROL_REG_ADDR(x)))

#define TW_DISABLE_INTERRUPTS(x) (outl(TW_CONTROL_DISABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))

#define TW_ENABLE_AND_CLEAR_INTERRUPTS(x) (outl(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT | TW_CONTROL_UNMASK_RESPONSE_INTERRUPT | TW_CONTROL_ENABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))

#define TW_MASK_COMMAND_INTERRUPT(x) (outl(TW_CONTROL_MASK_COMMAND_INTERRUPT, TW_CONTROL_REG_ADDR(x)))

#define TW_UNMASK_COMMAND_INTERRUPT(x) (outl(TW_CONTROL_UNMASK_COMMAND_INTERRUPT, TW_CONTROL_REG_ADDR(x)))

#define TW_CLEAR_ALL_INTERRUPTS(x)					\

	(outl(TW_STATUS_VALID_INTERRUPT, TW_CONTROL_REG_ADDR(x)))

#define TW_CLEAR_ATTENTION_INTERRUPT(x)					\

	(outl(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT, TW_CONTROL_REG_ADDR(x)))

#define TW_CLEAR_HOST_INTERRUPT(x)					\

	(outl(TW_CONTROL_CLEAR_HOST_INTERRUPT, TW_CONTROL_REG_ADDR(x)))

#define TW_DISABLE_INTERRUPTS(x)					\

	(outl(TW_CONTROL_DISABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))

#define TW_ENABLE_AND_CLEAR_INTERRUPTS(x)				\

	(outl(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT |			\

	      TW_CONTROL_UNMASK_RESPONSE_INTERRUPT |			\

	      TW_CONTROL_ENABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))

#define TW_MASK_COMMAND_INTERRUPT(x)					\

	(outl(TW_CONTROL_MASK_COMMAND_INTERRUPT, TW_CONTROL_REG_ADDR(x)))

#define TW_UNMASK_COMMAND_INTERRUPT(x)					\

	(outl(TW_CONTROL_UNMASK_COMMAND_INTERRUPT, TW_CONTROL_REG_ADDR(x)))

#define TW_SOFT_RESET(x) (outl(TW_CONTROL_ISSUE_SOFT_RESET |		\

			       TW_CONTROL_CLEAR_HOST_INTERRUPT |	\

			       TW_CONTROL_CLEAR_ATTENTION_INTERRUPT |	\