Commit 7d8bd91b authored by Maarten Lankhorst's avatar Maarten Lankhorst Committed by Ben Skeggs
Browse files

nvc0/vp: initial implementation of engine 



Will allow use of the engine if firmware (nvXX_fuc085) provided.

Signed-off-by: default avatarMaarten Lankhorst <maarten.lankhorst@canonical.com>
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 23c14ed2

drivers/gpu/drm/nouveau/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -185,6 +185,7 @@ nouveau-y += core/engine/software/nv10.o 
nouveau-y += core/engine/software/nv50.o

nouveau-y += core/engine/software/nvc0.o

nouveau-y += core/engine/vp/nv84.o

nouveau-y += core/engine/vp/nvc0.o

nouveau-y += core/engine/vp/nve0.o



# drm/core

drivers/gpu/drm/nouveau/core/engine/vp/nvc0.c

0 → 100644
+110 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2012 Maarten Lankhorst

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: Maarten Lankhorst

 */



#include <core/falcon.h>



#include <engine/vp.h>



struct nvc0_vp_priv {

	struct nouveau_falcon base;

};



/*******************************************************************************

 * VP object classes

 ******************************************************************************/



static struct nouveau_oclass

nvc0_vp_sclass[] = {

	{ 0x90b2, &nouveau_object_ofuncs },

	{},

};



/*******************************************************************************

 * PVP context

 ******************************************************************************/



static struct nouveau_oclass

nvc0_vp_cclass = {

	.handle = NV_ENGCTX(VP, 0xc0),

	.ofuncs = &(struct nouveau_ofuncs) {

		.ctor = _nouveau_falcon_context_ctor,

		.dtor = _nouveau_falcon_context_dtor,

		.init = _nouveau_falcon_context_init,

		.fini = _nouveau_falcon_context_fini,

		.rd32 = _nouveau_falcon_context_rd32,

		.wr32 = _nouveau_falcon_context_wr32,

	},

};



/*******************************************************************************

 * PVP engine/subdev functions

 ******************************************************************************/



static int

nvc0_vp_init(struct nouveau_object *object)

{

	struct nvc0_vp_priv *priv = (void *)object;

	int ret;



	ret = nouveau_falcon_init(&priv->base);

	if (ret)

		return ret;



	nv_wr32(priv, 0x085010, 0x0000fff2);

	nv_wr32(priv, 0x08501c, 0x0000fff2);

	return 0;

}



static int

nvc0_vp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,

	     struct nouveau_oclass *oclass, void *data, u32 size,

	     struct nouveau_object **pobject)

{

	struct nvc0_vp_priv *priv;

	int ret;



	ret = nouveau_falcon_create(parent, engine, oclass, 0x085000, true,

				    "PVP", "vp", &priv);

	*pobject = nv_object(priv);

	if (ret)

		return ret;



	nv_subdev(priv)->unit = 0x00020000;

	nv_engine(priv)->cclass = &nvc0_vp_cclass;

	nv_engine(priv)->sclass = nvc0_vp_sclass;

	return 0;

}



struct nouveau_oclass

nvc0_vp_oclass = {

	.handle = NV_ENGINE(VP, 0xc0),

	.ofuncs = &(struct nouveau_ofuncs) {

		.ctor = nvc0_vp_ctor,

		.dtor = _nouveau_falcon_dtor,

		.init = nvc0_vp_init,

		.fini = _nouveau_falcon_fini,

		.rd32 = _nouveau_falcon_rd32,

		.wr32 = _nouveau_falcon_wr32,

	},

};

drivers/gpu/drm/nouveau/core/include/engine/vp.h

+1 −0
Original line number Diff line number Diff line
@@ -2,6 +2,7 @@ 
#define __NOUVEAU_VP_H__



extern struct nouveau_oclass nv84_vp_oclass;

extern struct nouveau_oclass nvc0_vp_oclass;

extern struct nouveau_oclass nve0_vp_oclass;



#endif

drivers/gpu/drm/nouveau/core/subdev/device/nvc0.c

+8 −8
Original line number Diff line number Diff line
@@ -74,7 +74,7 @@ nvc0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;

		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;

		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;

		device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;

		device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;

		device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
@@ -102,7 +102,7 @@ nvc0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;

		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;

		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;

		device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;

		device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;

		device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
@@ -130,7 +130,7 @@ nvc0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;

		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;

		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;

		device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;

		device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;

		device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
@@ -158,7 +158,7 @@ nvc0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;

		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;

		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;

		device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;

		device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;

		device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
@@ -186,7 +186,7 @@ nvc0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;

		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;

		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;

		device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;

		device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;

		device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
@@ -214,7 +214,7 @@ nvc0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;

		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;

		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;

		device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;

		device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;

		device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
@@ -242,7 +242,7 @@ nvc0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;

		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;

		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;

		device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;

		device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;

		device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
@@ -270,7 +270,7 @@ nvc0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;

		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;

		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;

		device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;

		device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;

		device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;