Commit 7ccf5aa8 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/ih: store the full context id 



The contextID field (formerly known as src_data) of the IH
vector stores client specific information about an interrupt.
It was expanded from 32 bits to 128 on newer asics.  Expand the
src_id field to handle this.

Reviewed-by: default avatarHarry Wentland <harry.wentland@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d766e6a3

drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h

+3 −1
Original line number Diff line number Diff line
@@ -50,10 +50,12 @@ struct amdgpu_ih_ring { 
	dma_addr_t		rb_dma_addr; /* only used when use_bus_addr = true */

};



#define AMDGPU_IH_SRC_DATA_MAX_SIZE_DW 4



struct amdgpu_iv_entry {

	unsigned client_id;

	unsigned src_id;

	unsigned src_data;

	unsigned src_data[AMDGPU_IH_SRC_DATA_MAX_SIZE_DW];

	unsigned ring_id;

	unsigned vm_id;

	unsigned vm_id_src;

drivers/gpu/drm/amd/amdgpu/cik_ih.c

+1 −1
Original line number Diff line number Diff line
@@ -250,7 +250,7 @@ static void cik_ih_decode_iv(struct amdgpu_device *adev, 


	entry->client_id = AMDGPU_IH_CLIENTID_LEGACY;

	entry->src_id = dw[0] & 0xff;

	entry->src_data = dw[1] & 0xfffffff;

	entry->src_data[0] = dw[1] & 0xfffffff;

	entry->ring_id = dw[2] & 0xff;

	entry->vm_id = (dw[2] >> 8) & 0xff;

	entry->pas_id = (dw[2] >> 16) & 0xffff;

drivers/gpu/drm/amd/amdgpu/cz_ih.c

+1 −1
Original line number Diff line number Diff line
@@ -229,7 +229,7 @@ static void cz_ih_decode_iv(struct amdgpu_device *adev, 


	entry->client_id = AMDGPU_IH_CLIENTID_LEGACY;

	entry->src_id = dw[0] & 0xff;

	entry->src_data = dw[1] & 0xfffffff;

	entry->src_data[0] = dw[1] & 0xfffffff;

	entry->ring_id = dw[2] & 0xff;

	entry->vm_id = (dw[2] >> 8) & 0xff;

	entry->pas_id = (dw[2] >> 16) & 0xffff;

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

+5 −5
Original line number Diff line number Diff line
@@ -3398,7 +3398,7 @@ static int dce_v10_0_crtc_irq(struct amdgpu_device *adev, 
	uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);

	unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);



	switch (entry->src_data) {

	switch (entry->src_data[0]) {

	case 0: /* vblank */

		if (disp_int & interrupt_status_offsets[crtc].vblank)

			dce_v10_0_crtc_vblank_int_ack(adev, crtc);
@@ -3421,7 +3421,7 @@ static int dce_v10_0_crtc_irq(struct amdgpu_device *adev, 


		break;

	default:

		DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);

		DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);

		break;

	}
@@ -3435,12 +3435,12 @@ static int dce_v10_0_hpd_irq(struct amdgpu_device *adev, 
	uint32_t disp_int, mask;

	unsigned hpd;



	if (entry->src_data >= adev->mode_info.num_hpd) {

		DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);

	if (entry->src_data[0] >= adev->mode_info.num_hpd) {

		DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);

		return 0;

	}



	hpd = entry->src_data;

	hpd = entry->src_data[0];

	disp_int = RREG32(interrupt_status_offsets[hpd].reg);

	mask = interrupt_status_offsets[hpd].hpd;

drivers/gpu/drm/amd/amdgpu/dce_v11_0.c

+5 −5
Original line number Diff line number Diff line
@@ -3462,7 +3462,7 @@ static int dce_v11_0_crtc_irq(struct amdgpu_device *adev, 
	uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);

	unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);



	switch (entry->src_data) {

	switch (entry->src_data[0]) {

	case 0: /* vblank */

		if (disp_int & interrupt_status_offsets[crtc].vblank)

			dce_v11_0_crtc_vblank_int_ack(adev, crtc);
@@ -3485,7 +3485,7 @@ static int dce_v11_0_crtc_irq(struct amdgpu_device *adev, 


		break;

	default:

		DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);

		DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);

		break;

	}
@@ -3499,12 +3499,12 @@ static int dce_v11_0_hpd_irq(struct amdgpu_device *adev, 
	uint32_t disp_int, mask;

	unsigned hpd;



	if (entry->src_data >= adev->mode_info.num_hpd) {

		DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);

	if (entry->src_data[0] >= adev->mode_info.num_hpd) {

		DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);

		return 0;

	}



	hpd = entry->src_data;

	hpd = entry->src_data[0];

	disp_int = RREG32(interrupt_status_offsets[hpd].reg);

	mask = interrupt_status_offsets[hpd].hpd;